circuit RocketCore :
  module RocketCore :
    input const_clock : Clock
    input reset : UInt<1>
    input io_interrupts_debug : UInt<1>
    input io_interrupts_mtip : UInt<1>
    input io_interrupts_msip : UInt<1>
    input io_interrupts_meip : UInt<1>
    input io_interrupts_seip : UInt<1>
    input io_hartid : UInt<64>
    output io_imem_req_valid : UInt<1>
    output io_imem_req_bits_pc : UInt<40>
    output io_imem_req_bits_speculative : UInt<1>
    output io_imem_resp_ready : UInt<1>
    input io_imem_resp_valid : UInt<1>
    input io_imem_resp_bits_btb_valid : UInt<1>
    input io_imem_resp_bits_btb_bits_taken : UInt<1>
    input io_imem_resp_bits_btb_bits_mask : UInt<2>
    input io_imem_resp_bits_btb_bits_bridx : UInt<1>
    input io_imem_resp_bits_btb_bits_target : UInt<39>
    input io_imem_resp_bits_btb_bits_entry : UInt<6>
    input io_imem_resp_bits_btb_bits_bht_history : UInt<7>
    input io_imem_resp_bits_btb_bits_bht_value : UInt<2>
    input io_imem_resp_bits_pc : UInt<40>
    input io_imem_resp_bits_data : UInt<32>
    input io_imem_resp_bits_mask : UInt<2>
    input io_imem_resp_bits_xcpt_if : UInt<1>
    input io_imem_resp_bits_replay : UInt<1>
    output io_imem_btb_update_valid : UInt<1>
    output io_imem_btb_update_bits_prediction_valid : UInt<1>
    output io_imem_btb_update_bits_prediction_bits_taken : UInt<1>
    output io_imem_btb_update_bits_prediction_bits_mask : UInt<2>
    output io_imem_btb_update_bits_prediction_bits_bridx : UInt<1>
    output io_imem_btb_update_bits_prediction_bits_target : UInt<39>
    output io_imem_btb_update_bits_prediction_bits_entry : UInt<6>
    output io_imem_btb_update_bits_prediction_bits_bht_history : UInt<7>
    output io_imem_btb_update_bits_prediction_bits_bht_value : UInt<2>
    output io_imem_btb_update_bits_pc : UInt<39>
    output io_imem_btb_update_bits_target : UInt<39>
    output io_imem_btb_update_bits_taken : UInt<1>
    output io_imem_btb_update_bits_isValid : UInt<1>
    output io_imem_btb_update_bits_isJump : UInt<1>
    output io_imem_btb_update_bits_isReturn : UInt<1>
    output io_imem_btb_update_bits_br_pc : UInt<39>
    output io_imem_bht_update_valid : UInt<1>
    output io_imem_bht_update_bits_prediction_valid : UInt<1>
    output io_imem_bht_update_bits_prediction_bits_taken : UInt<1>
    output io_imem_bht_update_bits_prediction_bits_mask : UInt<2>
    output io_imem_bht_update_bits_prediction_bits_bridx : UInt<1>
    output io_imem_bht_update_bits_prediction_bits_target : UInt<39>
    output io_imem_bht_update_bits_prediction_bits_entry : UInt<6>
    output io_imem_bht_update_bits_prediction_bits_bht_history : UInt<7>
    output io_imem_bht_update_bits_prediction_bits_bht_value : UInt<2>
    output io_imem_bht_update_bits_pc : UInt<39>
    output io_imem_bht_update_bits_taken : UInt<1>
    output io_imem_bht_update_bits_mispredict : UInt<1>
    output io_imem_ras_update_valid : UInt<1>
    output io_imem_ras_update_bits_isCall : UInt<1>
    output io_imem_ras_update_bits_isReturn : UInt<1>
    output io_imem_ras_update_bits_returnAddr : UInt<39>
    output io_imem_ras_update_bits_prediction_valid : UInt<1>
    output io_imem_ras_update_bits_prediction_bits_taken : UInt<1>
    output io_imem_ras_update_bits_prediction_bits_mask : UInt<2>
    output io_imem_ras_update_bits_prediction_bits_bridx : UInt<1>
    output io_imem_ras_update_bits_prediction_bits_target : UInt<39>
    output io_imem_ras_update_bits_prediction_bits_entry : UInt<6>
    output io_imem_ras_update_bits_prediction_bits_bht_history : UInt<7>
    output io_imem_ras_update_bits_prediction_bits_bht_value : UInt<2>
    output io_imem_flush_icache : UInt<1>
    output io_imem_flush_tlb : UInt<1>
    input io_imem_npc : UInt<40>
    input io_imem_acquire : UInt<1>
    input io_dmem_req_ready : UInt<1>
    output io_dmem_req_valid : UInt<1>
    output io_dmem_req_bits_addr : UInt<40>
    output io_dmem_req_bits_tag : UInt<7>
    output io_dmem_req_bits_cmd : UInt<5>
    output io_dmem_req_bits_typ : UInt<3>
    output io_dmem_req_bits_phys : UInt<1>
    output io_dmem_req_bits_data : UInt<64>
    output io_dmem_s1_kill : UInt<1>
    output io_dmem_s1_data : UInt<64>
    input io_dmem_s2_nack : UInt<1>
    input io_dmem_acquire : UInt<1>
    input io_dmem_release : UInt<1>
    input io_dmem_resp_valid : UInt<1>
    input io_dmem_resp_bits_addr : UInt<40>
    input io_dmem_resp_bits_tag : UInt<7>
    input io_dmem_resp_bits_cmd : UInt<5>
    input io_dmem_resp_bits_typ : UInt<3>
    input io_dmem_resp_bits_data : UInt<64>
    input io_dmem_resp_bits_replay : UInt<1>
    input io_dmem_resp_bits_has_data : UInt<1>
    input io_dmem_resp_bits_data_word_bypass : UInt<64>
    input io_dmem_resp_bits_store_data : UInt<64>
    input io_dmem_replay_next : UInt<1>
    input io_dmem_xcpt_ma_ld : UInt<1>
    input io_dmem_xcpt_ma_st : UInt<1>
    input io_dmem_xcpt_pf_ld : UInt<1>
    input io_dmem_xcpt_pf_st : UInt<1>
    output io_dmem_invalidate_lr : UInt<1>
    input io_dmem_ordered : UInt<1>
    output io_ptw_ptbr_mode : UInt<4>
    output io_ptw_ptbr_asid : UInt<16>
    output io_ptw_ptbr_ppn : UInt<44>
    output io_ptw_invalidate : UInt<1>
    output io_ptw_status_debug : UInt<1>
    output io_ptw_status_isa : UInt<32>
    output io_ptw_status_prv : UInt<2>
    output io_ptw_status_sd : UInt<1>
    output io_ptw_status_zero2 : UInt<27>
    output io_ptw_status_sxl : UInt<2>
    output io_ptw_status_uxl : UInt<2>
    output io_ptw_status_sd_rv32 : UInt<1>
    output io_ptw_status_zero1 : UInt<8>
    output io_ptw_status_tsr : UInt<1>
    output io_ptw_status_tw : UInt<1>
    output io_ptw_status_tvm : UInt<1>
    output io_ptw_status_mxr : UInt<1>
    output io_ptw_status_pum : UInt<1>
    output io_ptw_status_mprv : UInt<1>
    output io_ptw_status_xs : UInt<2>
    output io_ptw_status_fs : UInt<2>
    output io_ptw_status_mpp : UInt<2>
    output io_ptw_status_hpp : UInt<2>
    output io_ptw_status_spp : UInt<1>
    output io_ptw_status_mpie : UInt<1>
    output io_ptw_status_hpie : UInt<1>
    output io_ptw_status_spie : UInt<1>
    output io_ptw_status_upie : UInt<1>
    output io_ptw_status_mie : UInt<1>
    output io_ptw_status_hie : UInt<1>
    output io_ptw_status_sie : UInt<1>
    output io_ptw_status_uie : UInt<1>
    output io_fpu_inst : UInt<32>
    output io_fpu_fromint_data : UInt<64>
    output io_fpu_fcsr_rm : UInt<3>
    input io_fpu_fcsr_flags_valid : UInt<1>
    input io_fpu_fcsr_flags_bits : UInt<5>
    input io_fpu_store_data : UInt<64>
    input io_fpu_toint_data : UInt<64>
    output io_fpu_dmem_resp_val : UInt<1>
    output io_fpu_dmem_resp_type : UInt<3>
    output io_fpu_dmem_resp_tag : UInt<5>
    output io_fpu_dmem_resp_data : UInt<64>
    output io_fpu_valid : UInt<1>
    input io_fpu_fcsr_rdy : UInt<1>
    input io_fpu_nack_mem : UInt<1>
    input io_fpu_illegal_rm : UInt<1>
    output io_fpu_killx : UInt<1>
    output io_fpu_killm : UInt<1>
    input io_fpu_dec_cmd : UInt<5>
    input io_fpu_dec_ldst : UInt<1>
    input io_fpu_dec_wen : UInt<1>
    input io_fpu_dec_ren1 : UInt<1>
    input io_fpu_dec_ren2 : UInt<1>
    input io_fpu_dec_ren3 : UInt<1>
    input io_fpu_dec_swap12 : UInt<1>
    input io_fpu_dec_swap23 : UInt<1>
    input io_fpu_dec_single : UInt<1>
    input io_fpu_dec_fromint : UInt<1>
    input io_fpu_dec_toint : UInt<1>
    input io_fpu_dec_fastpipe : UInt<1>
    input io_fpu_dec_fma : UInt<1>
    input io_fpu_dec_div : UInt<1>
    input io_fpu_dec_sqrt : UInt<1>
    input io_fpu_dec_wflags : UInt<1>
    input io_fpu_sboard_set : UInt<1>
    input io_fpu_sboard_clr : UInt<1>
    input io_fpu_sboard_clra : UInt<5>
    input io_rocc_cmd_ready : UInt<1>
    output io_rocc_cmd_valid : UInt<1>
    output io_rocc_cmd_bits_inst_funct : UInt<7>
    output io_rocc_cmd_bits_inst_rs2 : UInt<5>
    output io_rocc_cmd_bits_inst_rs1 : UInt<5>
    output io_rocc_cmd_bits_inst_xd : UInt<1>
    output io_rocc_cmd_bits_inst_xs1 : UInt<1>
    output io_rocc_cmd_bits_inst_xs2 : UInt<1>
    output io_rocc_cmd_bits_inst_rd : UInt<5>
    output io_rocc_cmd_bits_inst_opcode : UInt<7>
    output io_rocc_cmd_bits_rs1 : UInt<64>
    output io_rocc_cmd_bits_rs2 : UInt<64>
    output io_rocc_cmd_bits_status_debug : UInt<1>
    output io_rocc_cmd_bits_status_isa : UInt<32>
    output io_rocc_cmd_bits_status_prv : UInt<2>
    output io_rocc_cmd_bits_status_sd : UInt<1>
    output io_rocc_cmd_bits_status_zero2 : UInt<27>
    output io_rocc_cmd_bits_status_sxl : UInt<2>
    output io_rocc_cmd_bits_status_uxl : UInt<2>
    output io_rocc_cmd_bits_status_sd_rv32 : UInt<1>
    output io_rocc_cmd_bits_status_zero1 : UInt<8>
    output io_rocc_cmd_bits_status_tsr : UInt<1>
    output io_rocc_cmd_bits_status_tw : UInt<1>
    output io_rocc_cmd_bits_status_tvm : UInt<1>
    output io_rocc_cmd_bits_status_mxr : UInt<1>
    output io_rocc_cmd_bits_status_pum : UInt<1>
    output io_rocc_cmd_bits_status_mprv : UInt<1>
    output io_rocc_cmd_bits_status_xs : UInt<2>
    output io_rocc_cmd_bits_status_fs : UInt<2>
    output io_rocc_cmd_bits_status_mpp : UInt<2>
    output io_rocc_cmd_bits_status_hpp : UInt<2>
    output io_rocc_cmd_bits_status_spp : UInt<1>
    output io_rocc_cmd_bits_status_mpie : UInt<1>
    output io_rocc_cmd_bits_status_hpie : UInt<1>
    output io_rocc_cmd_bits_status_spie : UInt<1>
    output io_rocc_cmd_bits_status_upie : UInt<1>
    output io_rocc_cmd_bits_status_mie : UInt<1>
    output io_rocc_cmd_bits_status_hie : UInt<1>
    output io_rocc_cmd_bits_status_sie : UInt<1>
    output io_rocc_cmd_bits_status_uie : UInt<1>
    output io_rocc_resp_ready : UInt<1>
    input io_rocc_resp_valid : UInt<1>
    input io_rocc_resp_bits_rd : UInt<5>
    input io_rocc_resp_bits_data : UInt<64>
    output io_rocc_mem_req_ready : UInt<1>
    input io_rocc_mem_req_valid : UInt<1>
    input io_rocc_mem_req_bits_addr : UInt<40>
    input io_rocc_mem_req_bits_tag : UInt<7>
    input io_rocc_mem_req_bits_cmd : UInt<5>
    input io_rocc_mem_req_bits_typ : UInt<3>
    input io_rocc_mem_req_bits_phys : UInt<1>
    input io_rocc_mem_req_bits_data : UInt<64>
    input io_rocc_mem_s1_kill : UInt<1>
    input io_rocc_mem_s1_data : UInt<64>
    output io_rocc_mem_s2_nack : UInt<1>
    output io_rocc_mem_acquire : UInt<1>
    output io_rocc_mem_release : UInt<1>
    output io_rocc_mem_resp_valid : UInt<1>
    output io_rocc_mem_resp_bits_addr : UInt<40>
    output io_rocc_mem_resp_bits_tag : UInt<7>
    output io_rocc_mem_resp_bits_cmd : UInt<5>
    output io_rocc_mem_resp_bits_typ : UInt<3>
    output io_rocc_mem_resp_bits_data : UInt<64>
    output io_rocc_mem_resp_bits_replay : UInt<1>
    output io_rocc_mem_resp_bits_has_data : UInt<1>
    output io_rocc_mem_resp_bits_data_word_bypass : UInt<64>
    output io_rocc_mem_resp_bits_store_data : UInt<64>
    output io_rocc_mem_replay_next : UInt<1>
    output io_rocc_mem_xcpt_ma_ld : UInt<1>
    output io_rocc_mem_xcpt_ma_st : UInt<1>
    output io_rocc_mem_xcpt_pf_ld : UInt<1>
    output io_rocc_mem_xcpt_pf_st : UInt<1>
    input io_rocc_mem_invalidate_lr : UInt<1>
    output io_rocc_mem_ordered : UInt<1>
    input io_rocc_busy : UInt<1>
    input io_rocc_interrupt : UInt<1>
    output io_rocc_exception : UInt<1>

    input _T_3340 : UInt<64>
    input _T_3350 : UInt<64>
    output _T_3331__T_3340_addr : UInt<2>
    output _T_3331__T_3350_addr : UInt<2>
    output _T_3331__T_3340_en : UInt<1>
    output _T_3331__T_3350_en : UInt<1>
    output _T_3331__T_4200_addr : UInt<2>
    output _T_3331__T_4200_en : UInt<1>
    output _T_3331__T_4200_data : UInt<64>
    output _T_3331__T_4200_mask : UInt<1>


    skip
    node ibuf__T_439 = bits(io_imem_resp_bits_data, 15, 0) @[IBuf.scala 74:87]
    node ibuf__T_440 = cat(ibuf__T_439, ibuf__T_439) @[Cat.scala 30:58]
    node ibuf__T_441 = cat(io_imem_resp_bits_data, ibuf__T_440) @[Cat.scala 30:58]
    node ibuf__T_442 = shr(ibuf__T_441, 48) @[IBuf.scala 126:58]
    node ibuf__T_443 = cat(ibuf__T_442, ibuf__T_442) @[Cat.scala 30:58]
    node ibuf__T_444 = cat(ibuf__T_443, ibuf__T_443) @[Cat.scala 30:58]
    node ibuf__T_445 = cat(ibuf__T_444, ibuf__T_441) @[Cat.scala 30:58]
    skip
    reg ibuf_nBufValid : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ibuf_nBufValid) @[IBuf.scala 35:47]
    node _GEN_177 = pad(ibuf_nBufValid, 2) @[IBuf.scala 73:32]
    node ibuf__T_434 = add(UInt<2>("h2"), _GEN_177) @[IBuf.scala 73:32]
    node ibuf__T_435 = tail(ibuf__T_434, 1) @[IBuf.scala 73:32]
    skip
    node ibuf_pcWordBits = bits(io_imem_resp_bits_pc, 1, 1) @[Package.scala 44:13]
    node _GEN_178 = pad(ibuf_pcWordBits, 2) @[IBuf.scala 73:44]
    node ibuf__T_436 = sub(ibuf__T_435, _GEN_178) @[IBuf.scala 73:44]
    skip
    node ibuf__T_438 = tail(ibuf__T_436, 1) @[IBuf.scala 73:44]
    skip
    node ibuf__T_446 = shl(ibuf__T_438, 4) @[IBuf.scala 127:19]
    node ibuf__T_447 = dshl(ibuf__T_445, ibuf__T_446) @[IBuf.scala 127:10]
    node ibuf_icData = bits(ibuf__T_447, 95, 64) @[Package.scala 44:13]
    skip
    node ibuf__T_450 = shl(ibuf_nBufValid, 4) @[IBuf.scala 76:65]
    node ibuf__T_451 = dshl(UInt<32>("hffffffff"), ibuf__T_450) @[IBuf.scala 76:51]
    node ibuf_icMask = bits(ibuf__T_451, 31, 0) @[IBuf.scala 76:92]
    node ibuf__T_452 = and(ibuf_icData, ibuf_icMask) @[IBuf.scala 77:21]
    reg ibuf_buf_data : UInt<32>, const_clock with :
      reset => (UInt<1>("h0"), ibuf_buf_data) @[IBuf.scala 36:16]
    node ibuf__T_453 = not(ibuf_icMask) @[IBuf.scala 77:43]
    node ibuf__T_454 = and(ibuf_buf_data, ibuf__T_453) @[IBuf.scala 77:41]
    node ibuf_inst = or(ibuf__T_452, ibuf__T_454) @[IBuf.scala 77:30]
    skip
    node ibuf_RVCExpander__T_12 = bits(ibuf_inst, 1, 0) @[RVC.scala 162:20]
    node ibuf_RVCExpander__T_14 = neq(ibuf_RVCExpander__T_12, UInt<2>("h3")) @[RVC.scala 162:26]
    node ibuf_RVCExpander__T_15 = bits(ibuf_inst, 12, 5) @[RVC.scala 53:22]
    node ibuf_RVCExpander__T_17 = neq(ibuf_RVCExpander__T_15, UInt<8>("h0")) @[RVC.scala 53:29]
    node ibuf_RVCExpander__T_20 = mux(ibuf_RVCExpander__T_17, UInt<7>("h13"), UInt<7>("h1f")) @[RVC.scala 53:20]
    node ibuf_RVCExpander__T_21 = bits(ibuf_inst, 10, 7) @[RVC.scala 34:26]
    node ibuf_RVCExpander__T_22 = bits(ibuf_inst, 12, 11) @[RVC.scala 34:35]
    node ibuf_RVCExpander__T_23 = bits(ibuf_inst, 5, 5) @[RVC.scala 34:45]
    node ibuf_RVCExpander__T_24 = bits(ibuf_inst, 6, 6) @[RVC.scala 34:51]
    node ibuf_RVCExpander__T_26 = cat(ibuf_RVCExpander__T_24, UInt<2>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_27 = cat(ibuf_RVCExpander__T_21, ibuf_RVCExpander__T_22) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_28 = cat(ibuf_RVCExpander__T_27, ibuf_RVCExpander__T_23) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_29 = cat(ibuf_RVCExpander__T_28, ibuf_RVCExpander__T_26) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_33 = bits(ibuf_inst, 4, 2) @[RVC.scala 31:30]
    node ibuf_RVCExpander__T_34 = cat(UInt<2>("h1"), ibuf_RVCExpander__T_33) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_35 = cat(ibuf_RVCExpander__T_34, ibuf_RVCExpander__T_20) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_36 = cat(ibuf_RVCExpander__T_29, UInt<5>("h2")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_37 = cat(ibuf_RVCExpander__T_36, UInt<3>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_38 = cat(ibuf_RVCExpander__T_37, ibuf_RVCExpander__T_35) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_46 = bits(ibuf_inst, 31, 27) @[RVC.scala 20:101]
    node ibuf_RVCExpander__T_59 = bits(ibuf_inst, 6, 5) @[RVC.scala 36:20]
    node ibuf_RVCExpander__T_60 = bits(ibuf_inst, 12, 10) @[RVC.scala 36:28]
    node ibuf_RVCExpander__T_62 = cat(ibuf_RVCExpander__T_59, ibuf_RVCExpander__T_60) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_63 = cat(ibuf_RVCExpander__T_62, UInt<3>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_65 = bits(ibuf_inst, 9, 7) @[RVC.scala 30:30]
    node ibuf_RVCExpander__T_66 = cat(UInt<2>("h1"), ibuf_RVCExpander__T_65) @[Cat.scala 30:58]
    skip
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    node ibuf_RVCExpander__T_72 = cat(ibuf_RVCExpander__T_34, UInt<7>("h7")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_73 = cat(ibuf_RVCExpander__T_63, ibuf_RVCExpander__T_66) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_74 = cat(ibuf_RVCExpander__T_73, UInt<3>("h3")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_75 = cat(ibuf_RVCExpander__T_74, ibuf_RVCExpander__T_72) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_103 = cat(ibuf_RVCExpander__T_23, ibuf_RVCExpander__T_60) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_104 = cat(ibuf_RVCExpander__T_103, ibuf_RVCExpander__T_26) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_113 = cat(ibuf_RVCExpander__T_34, UInt<7>("h3")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_114 = cat(ibuf_RVCExpander__T_104, ibuf_RVCExpander__T_66) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_115 = cat(ibuf_RVCExpander__T_114, UInt<3>("h2")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_116 = cat(ibuf_RVCExpander__T_115, ibuf_RVCExpander__T_113) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_155 = cat(ibuf_RVCExpander__T_74, ibuf_RVCExpander__T_113) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_185 = shr(ibuf_RVCExpander__T_104, 5) @[RVC.scala 63:32]
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    node ibuf_RVCExpander__T_200 = bits(ibuf_RVCExpander__T_104, 4, 0) @[RVC.scala 63:66]
    node ibuf_RVCExpander__T_202 = cat(UInt<3>("h2"), ibuf_RVCExpander__T_200) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_203 = cat(ibuf_RVCExpander__T_202, UInt<7>("h2f")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_204 = cat(ibuf_RVCExpander__T_185, ibuf_RVCExpander__T_34) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_205 = cat(ibuf_RVCExpander__T_204, ibuf_RVCExpander__T_66) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_206 = cat(ibuf_RVCExpander__T_205, ibuf_RVCExpander__T_203) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_234 = shr(ibuf_RVCExpander__T_63, 5) @[RVC.scala 66:30]
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    node ibuf_RVCExpander__T_247 = bits(ibuf_RVCExpander__T_63, 4, 0) @[RVC.scala 66:64]
    node ibuf_RVCExpander__T_249 = cat(UInt<3>("h3"), ibuf_RVCExpander__T_247) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_250 = cat(ibuf_RVCExpander__T_249, UInt<7>("h27")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_251 = cat(ibuf_RVCExpander__T_234, ibuf_RVCExpander__T_34) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_252 = cat(ibuf_RVCExpander__T_251, ibuf_RVCExpander__T_66) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_253 = cat(ibuf_RVCExpander__T_252, ibuf_RVCExpander__T_250) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_301 = cat(ibuf_RVCExpander__T_202, UInt<7>("h23")) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_304 = cat(ibuf_RVCExpander__T_205, ibuf_RVCExpander__T_301) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_348 = cat(ibuf_RVCExpander__T_249, UInt<7>("h23")) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_351 = cat(ibuf_RVCExpander__T_252, ibuf_RVCExpander__T_348) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_374 = bits(ibuf_inst, 12, 12) @[RVC.scala 43:30]
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    node ibuf_RVCExpander__T_378 = mux(ibuf_RVCExpander__T_374, UInt<7>("h7f"), UInt<7>("h0")) @[Bitwise.scala 71:12]
    node ibuf_RVCExpander__T_379 = bits(ibuf_inst, 6, 2) @[RVC.scala 43:38]
    node ibuf_RVCExpander__T_380 = cat(ibuf_RVCExpander__T_378, ibuf_RVCExpander__T_379) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_381 = bits(ibuf_inst, 11, 7) @[RVC.scala 33:13]
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    node ibuf_RVCExpander__T_385 = cat(ibuf_RVCExpander__T_381, UInt<7>("h13")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_386 = cat(ibuf_RVCExpander__T_380, ibuf_RVCExpander__T_381) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_387 = cat(ibuf_RVCExpander__T_386, UInt<3>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_388 = cat(ibuf_RVCExpander__T_387, ibuf_RVCExpander__T_385) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_409 = neq(ibuf_RVCExpander__T_381, UInt<5>("h0")) @[RVC.scala 77:24]
    node ibuf_RVCExpander__T_412 = mux(ibuf_RVCExpander__T_409, UInt<7>("h1b"), UInt<7>("h1f")) @[RVC.scala 77:20]
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    node ibuf_RVCExpander__T_423 = cat(ibuf_RVCExpander__T_381, ibuf_RVCExpander__T_412) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_426 = cat(ibuf_RVCExpander__T_387, ibuf_RVCExpander__T_423) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_457 = cat(ibuf_RVCExpander__T_380, UInt<5>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_458 = cat(ibuf_RVCExpander__T_457, UInt<3>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_459 = cat(ibuf_RVCExpander__T_458, ibuf_RVCExpander__T_385) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_486 = neq(ibuf_RVCExpander__T_380, UInt<12>("h0")) @[RVC.scala 90:29]
    node ibuf_RVCExpander__T_489 = mux(ibuf_RVCExpander__T_486, UInt<7>("h37"), UInt<7>("h3f")) @[RVC.scala 90:20]
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    node ibuf_RVCExpander__T_494 = mux(ibuf_RVCExpander__T_374, UInt<15>("h7fff"), UInt<15>("h0")) @[Bitwise.scala 71:12]
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    node ibuf_RVCExpander__T_497 = cat(ibuf_RVCExpander__T_494, ibuf_RVCExpander__T_379) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_498 = cat(ibuf_RVCExpander__T_497, UInt<12>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_499 = bits(ibuf_RVCExpander__T_498, 31, 12) @[RVC.scala 91:31]
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    node ibuf_RVCExpander__T_501 = cat(ibuf_RVCExpander__T_499, ibuf_RVCExpander__T_381) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_502 = cat(ibuf_RVCExpander__T_501, ibuf_RVCExpander__T_489) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_523 = eq(ibuf_RVCExpander__T_381, UInt<5>("h0")) @[RVC.scala 92:14]
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    node ibuf_RVCExpander__T_526 = eq(ibuf_RVCExpander__T_381, UInt<5>("h2")) @[RVC.scala 92:27]
    node ibuf_RVCExpander__T_527 = or(ibuf_RVCExpander__T_523, ibuf_RVCExpander__T_526) @[RVC.scala 92:21]
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    node ibuf_RVCExpander__T_539 = mux(ibuf_RVCExpander__T_486, UInt<7>("h13"), UInt<7>("h1f")) @[RVC.scala 86:20]
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    node ibuf_RVCExpander__T_544 = mux(ibuf_RVCExpander__T_374, UInt<3>("h7"), UInt<3>("h0")) @[Bitwise.scala 71:12]
    node ibuf_RVCExpander__T_545 = bits(ibuf_inst, 4, 3) @[RVC.scala 42:42]
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    node ibuf_RVCExpander__T_547 = bits(ibuf_inst, 2, 2) @[RVC.scala 42:56]
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    node ibuf_RVCExpander__T_550 = cat(ibuf_RVCExpander__T_547, ibuf_RVCExpander__T_24) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_551 = cat(ibuf_RVCExpander__T_550, UInt<4>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_552 = cat(ibuf_RVCExpander__T_544, ibuf_RVCExpander__T_545) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_553 = cat(ibuf_RVCExpander__T_552, ibuf_RVCExpander__T_23) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_554 = cat(ibuf_RVCExpander__T_553, ibuf_RVCExpander__T_551) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_558 = cat(ibuf_RVCExpander__T_381, ibuf_RVCExpander__T_539) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_559 = cat(ibuf_RVCExpander__T_554, ibuf_RVCExpander__T_381) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_560 = cat(ibuf_RVCExpander__T_559, UInt<3>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_561 = cat(ibuf_RVCExpander__T_560, ibuf_RVCExpander__T_558) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_580_bits = mux(ibuf_RVCExpander__T_527, ibuf_RVCExpander__T_561, ibuf_RVCExpander__T_502) @[RVC.scala 92:10]
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    node ibuf_RVCExpander__T_580_rd = mux(ibuf_RVCExpander__T_527, ibuf_RVCExpander__T_381, ibuf_RVCExpander__T_381) @[RVC.scala 92:10]
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    node ibuf_RVCExpander__T_580_rs2 = mux(ibuf_RVCExpander__T_527, ibuf_RVCExpander__T_34, ibuf_RVCExpander__T_34) @[RVC.scala 92:10]
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    node ibuf_RVCExpander__T_580_rs3 = mux(ibuf_RVCExpander__T_527, ibuf_RVCExpander__T_46, ibuf_RVCExpander__T_46) @[RVC.scala 92:10]
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    node ibuf_RVCExpander__T_588 = cat(ibuf_RVCExpander__T_374, ibuf_RVCExpander__T_379) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_597 = cat(ibuf_RVCExpander__T_66, UInt<7>("h13")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_598 = cat(ibuf_RVCExpander__T_588, ibuf_RVCExpander__T_66) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_599 = cat(ibuf_RVCExpander__T_598, UInt<3>("h5")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_600 = cat(ibuf_RVCExpander__T_599, ibuf_RVCExpander__T_597) @[Cat.scala 30:58]
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    node _GEN_179 = pad(ibuf_RVCExpander__T_600, 31) @[RVC.scala 99:23]
    node ibuf_RVCExpander__T_617 = or(_GEN_179, UInt<31>("h40000000")) @[RVC.scala 99:23]
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    node ibuf_RVCExpander__T_634 = cat(ibuf_RVCExpander__T_380, ibuf_RVCExpander__T_66) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_635 = cat(ibuf_RVCExpander__T_634, UInt<3>("h7")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_636 = cat(ibuf_RVCExpander__T_635, ibuf_RVCExpander__T_597) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_647 = cat(ibuf_RVCExpander__T_374, ibuf_RVCExpander__T_59) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_649 = and(ibuf_RVCExpander__T_647, UInt<3>("h3")) @[Package.scala 18:26]
    node ibuf_RVCExpander__T_651 = geq(ibuf_RVCExpander__T_647, UInt<3>("h4")) @[Package.scala 19:17]
    node ibuf_RVCExpander__T_653 = and(ibuf_RVCExpander__T_649, UInt<3>("h1")) @[Package.scala 18:26]
    node ibuf_RVCExpander__T_655 = geq(ibuf_RVCExpander__T_649, UInt<3>("h2")) @[Package.scala 19:17]
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    node ibuf_RVCExpander__T_659 = geq(ibuf_RVCExpander__T_653, UInt<3>("h1")) @[Package.scala 19:17]
    node ibuf_RVCExpander__T_660 = mux(ibuf_RVCExpander__T_659, UInt<2>("h3"), UInt<2>("h2")) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_666 = mux(ibuf_RVCExpander__T_655, ibuf_RVCExpander__T_660, UInt<2>("h0")) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_675 = mux(ibuf_RVCExpander__T_659, UInt<3>("h7"), UInt<3>("h6")) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_680 = mux(ibuf_RVCExpander__T_659, UInt<3>("h4"), UInt<3>("h0")) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_681 = mux(ibuf_RVCExpander__T_655, ibuf_RVCExpander__T_675, ibuf_RVCExpander__T_680) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_682 = mux(ibuf_RVCExpander__T_651, pad(ibuf_RVCExpander__T_666, 3), ibuf_RVCExpander__T_681) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_685 = eq(ibuf_RVCExpander__T_59, UInt<2>("h0")) @[RVC.scala 103:30]
    node ibuf_RVCExpander__T_688 = mux(ibuf_RVCExpander__T_685, UInt<31>("h40000000"), UInt<31>("h0")) @[RVC.scala 103:22]
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    node ibuf_RVCExpander__T_692 = mux(ibuf_RVCExpander__T_374, UInt<7>("h3b"), UInt<7>("h33")) @[RVC.scala 104:22]
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    node ibuf_RVCExpander__T_702 = cat(ibuf_RVCExpander__T_66, ibuf_RVCExpander__T_692) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_703 = cat(ibuf_RVCExpander__T_34, ibuf_RVCExpander__T_66) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_704 = cat(ibuf_RVCExpander__T_703, ibuf_RVCExpander__T_682) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_705 = cat(ibuf_RVCExpander__T_704, ibuf_RVCExpander__T_702) @[Cat.scala 30:58]
    node _GEN_180 = pad(ibuf_RVCExpander__T_705, 31) @[RVC.scala 105:43]
    node ibuf_RVCExpander__T_706 = or(_GEN_180, ibuf_RVCExpander__T_688) @[RVC.scala 105:43]
    node ibuf_RVCExpander__T_707 = bits(ibuf_inst, 11, 10) @[RVC.scala 107:42]
    node ibuf_RVCExpander__T_709 = and(ibuf_RVCExpander__T_707, UInt<2>("h1")) @[Package.scala 18:26]
    node ibuf_RVCExpander__T_711 = geq(ibuf_RVCExpander__T_707, UInt<2>("h2")) @[Package.scala 19:17]
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    node ibuf_RVCExpander__T_715 = geq(ibuf_RVCExpander__T_709, UInt<2>("h1")) @[Package.scala 19:17]
    node ibuf_RVCExpander__T_716 = mux(ibuf_RVCExpander__T_715, pad(ibuf_RVCExpander__T_706, 32), ibuf_RVCExpander__T_636) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_721 = mux(ibuf_RVCExpander__T_715, ibuf_RVCExpander__T_617, pad(ibuf_RVCExpander__T_600, 31)) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_722 = mux(ibuf_RVCExpander__T_711, ibuf_RVCExpander__T_716, pad(ibuf_RVCExpander__T_721, 32)) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_749 = mux(ibuf_RVCExpander__T_374, UInt<10>("h3ff"), UInt<10>("h0")) @[Bitwise.scala 71:12]
    node ibuf_RVCExpander__T_750 = bits(ibuf_inst, 8, 8) @[RVC.scala 44:36]
    node ibuf_RVCExpander__T_751 = bits(ibuf_inst, 10, 9) @[RVC.scala 44:42]
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    node ibuf_RVCExpander__T_753 = bits(ibuf_inst, 7, 7) @[RVC.scala 44:57]
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    node ibuf_RVCExpander__T_755 = bits(ibuf_inst, 11, 11) @[RVC.scala 44:69]
    node ibuf_RVCExpander__T_756 = bits(ibuf_inst, 5, 3) @[RVC.scala 44:76]
    node ibuf_RVCExpander__T_758 = cat(ibuf_RVCExpander__T_756, UInt<1>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_759 = cat(ibuf_RVCExpander__T_547, ibuf_RVCExpander__T_755) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_760 = cat(ibuf_RVCExpander__T_759, ibuf_RVCExpander__T_758) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_761 = cat(ibuf_RVCExpander__T_24, ibuf_RVCExpander__T_753) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_762 = cat(ibuf_RVCExpander__T_749, ibuf_RVCExpander__T_750) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_763 = cat(ibuf_RVCExpander__T_762, ibuf_RVCExpander__T_751) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_764 = cat(ibuf_RVCExpander__T_763, ibuf_RVCExpander__T_761) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_765 = cat(ibuf_RVCExpander__T_764, ibuf_RVCExpander__T_760) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_766 = bits(ibuf_RVCExpander__T_765, 20, 20) @[RVC.scala 94:26]
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    node ibuf_RVCExpander__T_788 = bits(ibuf_RVCExpander__T_765, 10, 1) @[RVC.scala 94:36]
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    node ibuf_RVCExpander__T_810 = bits(ibuf_RVCExpander__T_765, 11, 11) @[RVC.scala 94:48]
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    node ibuf_RVCExpander__T_832 = bits(ibuf_RVCExpander__T_765, 19, 12) @[RVC.scala 94:58]
    node ibuf_RVCExpander__T_835 = cat(ibuf_RVCExpander__T_832, UInt<5>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_836 = cat(ibuf_RVCExpander__T_835, UInt<7>("h6f")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_837 = cat(ibuf_RVCExpander__T_766, ibuf_RVCExpander__T_788) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_838 = cat(ibuf_RVCExpander__T_837, ibuf_RVCExpander__T_810) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_839 = cat(ibuf_RVCExpander__T_838, ibuf_RVCExpander__T_836) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_864 = mux(ibuf_RVCExpander__T_374, UInt<5>("h1f"), UInt<5>("h0")) @[Bitwise.scala 71:12]
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    node ibuf_RVCExpander__T_870 = cat(ibuf_RVCExpander__T_707, ibuf_RVCExpander__T_545) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_871 = cat(ibuf_RVCExpander__T_870, UInt<1>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_872 = cat(ibuf_RVCExpander__T_864, ibuf_RVCExpander__T_59) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_873 = cat(ibuf_RVCExpander__T_872, ibuf_RVCExpander__T_547) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_874 = cat(ibuf_RVCExpander__T_873, ibuf_RVCExpander__T_871) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_875 = bits(ibuf_RVCExpander__T_874, 12, 12) @[RVC.scala 95:29]
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    node ibuf_RVCExpander__T_891 = bits(ibuf_RVCExpander__T_874, 10, 5) @[RVC.scala 95:39]
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    node ibuf_RVCExpander__T_912 = bits(ibuf_RVCExpander__T_874, 4, 1) @[RVC.scala 95:72]
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    node ibuf_RVCExpander__T_928 = bits(ibuf_RVCExpander__T_874, 11, 11) @[RVC.scala 95:83]
    node ibuf_RVCExpander__T_930 = cat(ibuf_RVCExpander__T_928, UInt<7>("h63")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_931 = cat(UInt<3>("h0"), ibuf_RVCExpander__T_912) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_932 = cat(ibuf_RVCExpander__T_931, ibuf_RVCExpander__T_930) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_933 = cat(UInt<5>("h0"), ibuf_RVCExpander__T_66) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_934 = cat(ibuf_RVCExpander__T_875, ibuf_RVCExpander__T_891) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_935 = cat(ibuf_RVCExpander__T_934, ibuf_RVCExpander__T_933) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_936 = cat(ibuf_RVCExpander__T_935, ibuf_RVCExpander__T_932) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1028 = cat(UInt<3>("h1"), ibuf_RVCExpander__T_912) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1029 = cat(ibuf_RVCExpander__T_1028, ibuf_RVCExpander__T_930) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1033 = cat(ibuf_RVCExpander__T_935, ibuf_RVCExpander__T_1029) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1060 = cat(ibuf_RVCExpander__T_588, ibuf_RVCExpander__T_381) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1061 = cat(ibuf_RVCExpander__T_1060, UInt<3>("h1")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1062 = cat(ibuf_RVCExpander__T_1061, ibuf_RVCExpander__T_385) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1083 = cat(ibuf_RVCExpander__T_59, UInt<3>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1084 = cat(ibuf_RVCExpander__T_33, ibuf_RVCExpander__T_374) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1085 = cat(ibuf_RVCExpander__T_1084, ibuf_RVCExpander__T_1083) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1090 = cat(ibuf_RVCExpander__T_381, UInt<7>("h7")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1091 = cat(ibuf_RVCExpander__T_1085, UInt<5>("h2")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1092 = cat(ibuf_RVCExpander__T_1091, UInt<3>("h3")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1093 = cat(ibuf_RVCExpander__T_1092, ibuf_RVCExpander__T_1090) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1110 = bits(ibuf_inst, 3, 2) @[RVC.scala 37:22]
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    node ibuf_RVCExpander__T_1112 = bits(ibuf_inst, 6, 4) @[RVC.scala 37:37]
    node ibuf_RVCExpander__T_1114 = cat(ibuf_RVCExpander__T_1112, UInt<2>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1115 = cat(ibuf_RVCExpander__T_1110, ibuf_RVCExpander__T_374) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1116 = cat(ibuf_RVCExpander__T_1115, ibuf_RVCExpander__T_1114) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1121 = cat(ibuf_RVCExpander__T_381, UInt<7>("h3")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1122 = cat(ibuf_RVCExpander__T_1116, UInt<5>("h2")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1123 = cat(ibuf_RVCExpander__T_1122, UInt<3>("h2")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1124 = cat(ibuf_RVCExpander__T_1123, ibuf_RVCExpander__T_1121) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1155 = cat(ibuf_RVCExpander__T_1092, ibuf_RVCExpander__T_1121) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1177 = cat(ibuf_RVCExpander__T_381, UInt<7>("h33")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1178 = cat(ibuf_RVCExpander__T_379, UInt<5>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1179 = cat(ibuf_RVCExpander__T_1178, UInt<3>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1180 = cat(ibuf_RVCExpander__T_1179, ibuf_RVCExpander__T_1177) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1203 = cat(ibuf_RVCExpander__T_379, ibuf_RVCExpander__T_381) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1204 = cat(ibuf_RVCExpander__T_1203, UInt<3>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1205 = cat(ibuf_RVCExpander__T_1204, ibuf_RVCExpander__T_1177) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1230 = cat(ibuf_RVCExpander__T_1204, UInt<12>("h67")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1231 = shr(ibuf_RVCExpander__T_1230, 7) @[RVC.scala 132:29]
    node ibuf_RVCExpander__T_1233 = cat(ibuf_RVCExpander__T_1231, UInt<7>("h1f")) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1237 = mux(ibuf_RVCExpander__T_409, ibuf_RVCExpander__T_1230, ibuf_RVCExpander__T_1233) @[RVC.scala 133:33]
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    node ibuf_RVCExpander__T_1256 = neq(ibuf_RVCExpander__T_379, UInt<5>("h0")) @[RVC.scala 134:27]
    node ibuf_RVCExpander__T_1191_bits = pad(ibuf_RVCExpander__T_1180, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1248_bits = pad(ibuf_RVCExpander__T_1237, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1257_bits = mux(ibuf_RVCExpander__T_1256, ibuf_RVCExpander__T_1191_bits, ibuf_RVCExpander__T_1248_bits) @[RVC.scala 134:22]
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    node ibuf_RVCExpander__T_1257_rd = mux(ibuf_RVCExpander__T_1256, ibuf_RVCExpander__T_381, UInt<5>("h0")) @[RVC.scala 134:22]
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    node ibuf_RVCExpander__T_1257_rs1 = mux(ibuf_RVCExpander__T_1256, UInt<5>("h0"), ibuf_RVCExpander__T_381) @[RVC.scala 134:22]
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    node ibuf_RVCExpander__T_1257_rs2 = mux(ibuf_RVCExpander__T_1256, ibuf_RVCExpander__T_379, ibuf_RVCExpander__T_379) @[RVC.scala 134:22]
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    node ibuf_RVCExpander__T_1257_rs3 = mux(ibuf_RVCExpander__T_1256, ibuf_RVCExpander__T_46, ibuf_RVCExpander__T_46) @[RVC.scala 134:22]
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    node ibuf_RVCExpander__T_1271 = cat(ibuf_RVCExpander__T_1204, UInt<12>("he7")) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1274 = cat(ibuf_RVCExpander__T_1231, UInt<7>("h73")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1276 = or(ibuf_RVCExpander__T_1274, UInt<25>("h100000")) @[RVC.scala 136:47]
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    node ibuf_RVCExpander__T_1280 = mux(ibuf_RVCExpander__T_409, ibuf_RVCExpander__T_1271, ibuf_RVCExpander__T_1276) @[RVC.scala 137:33]
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    node ibuf_RVCExpander__T_1216_bits = pad(ibuf_RVCExpander__T_1205, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1291_bits = pad(ibuf_RVCExpander__T_1280, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1300_bits = mux(ibuf_RVCExpander__T_1256, ibuf_RVCExpander__T_1216_bits, ibuf_RVCExpander__T_1291_bits) @[RVC.scala 138:25]
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    node ibuf_RVCExpander__T_1300_rd = mux(ibuf_RVCExpander__T_1256, ibuf_RVCExpander__T_381, UInt<5>("h1")) @[RVC.scala 138:25]
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    node ibuf_RVCExpander__T_1300_rs1 = mux(ibuf_RVCExpander__T_1256, ibuf_RVCExpander__T_381, ibuf_RVCExpander__T_381) @[RVC.scala 138:25]
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    node ibuf_RVCExpander__T_1307_bits = mux(ibuf_RVCExpander__T_374, ibuf_RVCExpander__T_1300_bits, ibuf_RVCExpander__T_1257_bits) @[RVC.scala 139:10]
    node ibuf_RVCExpander__T_1307_rd = mux(ibuf_RVCExpander__T_374, ibuf_RVCExpander__T_1300_rd, ibuf_RVCExpander__T_1257_rd) @[RVC.scala 139:10]
    node ibuf_RVCExpander__T_1307_rs1 = mux(ibuf_RVCExpander__T_374, ibuf_RVCExpander__T_1300_rs1, ibuf_RVCExpander__T_1257_rs1) @[RVC.scala 139:10]
    node ibuf_RVCExpander__T_1307_rs2 = mux(ibuf_RVCExpander__T_374, ibuf_RVCExpander__T_1257_rs2, ibuf_RVCExpander__T_1257_rs2) @[RVC.scala 139:10]
    node ibuf_RVCExpander__T_1307_rs3 = mux(ibuf_RVCExpander__T_374, ibuf_RVCExpander__T_1257_rs3, ibuf_RVCExpander__T_1257_rs3) @[RVC.scala 139:10]
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    node ibuf_RVCExpander__T_1316 = cat(ibuf_RVCExpander__T_65, ibuf_RVCExpander__T_60) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1317 = cat(ibuf_RVCExpander__T_1316, UInt<3>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1318 = shr(ibuf_RVCExpander__T_1317, 5) @[RVC.scala 123:34]
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    node ibuf_RVCExpander__T_1327 = bits(ibuf_RVCExpander__T_1317, 4, 0) @[RVC.scala 123:67]
    node ibuf_RVCExpander__T_1329 = cat(UInt<3>("h3"), ibuf_RVCExpander__T_1327) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1330 = cat(ibuf_RVCExpander__T_1329, UInt<7>("h27")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1331 = cat(ibuf_RVCExpander__T_1318, ibuf_RVCExpander__T_379) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1332 = cat(ibuf_RVCExpander__T_1331, UInt<5>("h2")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1333 = cat(ibuf_RVCExpander__T_1332, ibuf_RVCExpander__T_1330) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1350 = bits(ibuf_inst, 8, 7) @[RVC.scala 39:22]
    node ibuf_RVCExpander__T_1351 = bits(ibuf_inst, 12, 9) @[RVC.scala 39:30]
    node ibuf_RVCExpander__T_1353 = cat(ibuf_RVCExpander__T_1350, ibuf_RVCExpander__T_1351) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1354 = cat(ibuf_RVCExpander__T_1353, UInt<2>("h0")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1355 = shr(ibuf_RVCExpander__T_1354, 5) @[RVC.scala 122:33]
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    node ibuf_RVCExpander__T_1364 = bits(ibuf_RVCExpander__T_1354, 4, 0) @[RVC.scala 122:66]
    node ibuf_RVCExpander__T_1366 = cat(UInt<3>("h2"), ibuf_RVCExpander__T_1364) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1367 = cat(ibuf_RVCExpander__T_1366, UInt<7>("h23")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1368 = cat(ibuf_RVCExpander__T_1355, ibuf_RVCExpander__T_379) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1369 = cat(ibuf_RVCExpander__T_1368, UInt<5>("h2")) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1370 = cat(ibuf_RVCExpander__T_1369, ibuf_RVCExpander__T_1367) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1404 = cat(ibuf_RVCExpander__T_1329, UInt<7>("h23")) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1407 = cat(ibuf_RVCExpander__T_1332, ibuf_RVCExpander__T_1404) @[Cat.scala 30:58]
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    node ibuf_RVCExpander__T_1425 = bits(ibuf_inst, 19, 15) @[RVC.scala 20:57]
    node ibuf_RVCExpander__T_1426 = bits(ibuf_inst, 24, 20) @[RVC.scala 20:79]
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    node ibuf_RVCExpander__T_1553 = bits(ibuf_inst, 15, 13) @[RVC.scala 150:20]
    node ibuf_RVCExpander__T_1554 = cat(ibuf_RVCExpander__T_12, ibuf_RVCExpander__T_1553) @[Cat.scala 30:58]
    node ibuf_RVCExpander__T_1556 = and(ibuf_RVCExpander__T_1554, UInt<5>("hf")) @[Package.scala 18:26]
    node ibuf_RVCExpander__T_1558 = geq(ibuf_RVCExpander__T_1554, UInt<5>("h10")) @[Package.scala 19:17]
    node ibuf_RVCExpander__T_1560 = and(ibuf_RVCExpander__T_1556, UInt<5>("h7")) @[Package.scala 18:26]
    node ibuf_RVCExpander__T_1562 = geq(ibuf_RVCExpander__T_1556, UInt<5>("h8")) @[Package.scala 19:17]
    node ibuf_RVCExpander__T_1564 = and(ibuf_RVCExpander__T_1560, UInt<5>("h3")) @[Package.scala 18:26]
    node ibuf_RVCExpander__T_1566 = geq(ibuf_RVCExpander__T_1560, UInt<5>("h4")) @[Package.scala 19:17]
    node ibuf_RVCExpander__T_1568 = and(ibuf_RVCExpander__T_1564, UInt<5>("h1")) @[Package.scala 18:26]
    node ibuf_RVCExpander__T_1570 = geq(ibuf_RVCExpander__T_1564, UInt<5>("h2")) @[Package.scala 19:17]
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    node ibuf_RVCExpander__T_1574 = geq(ibuf_RVCExpander__T_1568, UInt<5>("h1")) @[Package.scala 19:17]
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    node ibuf_RVCExpander__T_1575_rd = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_381, ibuf_RVCExpander__T_381) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1575_rs1 = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_1425, ibuf_RVCExpander__T_1425) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1575_rs2 = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_1426, ibuf_RVCExpander__T_1426) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1575_rs3 = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_46, ibuf_RVCExpander__T_46) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1591_rd = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1575_rd, ibuf_RVCExpander__T_1575_rd) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1591_rs1 = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1575_rs1, ibuf_RVCExpander__T_1575_rs1) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1591_rs2 = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1575_rs2, ibuf_RVCExpander__T_1575_rs2) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1591_rs3 = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1575_rs3, ibuf_RVCExpander__T_1575_rs3) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1627_rd = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1591_rd, ibuf_RVCExpander__T_1591_rd) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1627_rs1 = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1591_rs1, ibuf_RVCExpander__T_1591_rs1) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1627_rs2 = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1591_rs2, ibuf_RVCExpander__T_1591_rs2) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1627_rs3 = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1591_rs3, ibuf_RVCExpander__T_1591_rs3) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1418_bits = pad(ibuf_RVCExpander__T_1407, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1381_bits = pad(ibuf_RVCExpander__T_1370, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1645_bits = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_1418_bits, ibuf_RVCExpander__T_1381_bits) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1645_rs2 = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_379, ibuf_RVCExpander__T_379) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1344_bits = pad(ibuf_RVCExpander__T_1333, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1655_bits = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_1344_bits, ibuf_RVCExpander__T_1307_bits) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1655_rd = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_381, ibuf_RVCExpander__T_1307_rd) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1655_rs1 = mux(ibuf_RVCExpander__T_1574, UInt<5>("h2"), ibuf_RVCExpander__T_1307_rs1) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1655_rs2 = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_379, ibuf_RVCExpander__T_1307_rs2) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1655_rs3 = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_46, ibuf_RVCExpander__T_1307_rs3) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1661_bits = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1645_bits, ibuf_RVCExpander__T_1655_bits) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1661_rd = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1575_rd, ibuf_RVCExpander__T_1655_rd) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1661_rs1 = mux(ibuf_RVCExpander__T_1570, UInt<5>("h2"), ibuf_RVCExpander__T_1655_rs1) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1661_rs2 = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1645_rs2, ibuf_RVCExpander__T_1655_rs2) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1661_rs3 = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1575_rs3, ibuf_RVCExpander__T_1655_rs3) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1166_bits = pad(ibuf_RVCExpander__T_1155, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1135_bits = pad(ibuf_RVCExpander__T_1124, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1675_bits = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_1166_bits, ibuf_RVCExpander__T_1135_bits) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1104_bits = pad(ibuf_RVCExpander__T_1093, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1073_bits = pad(ibuf_RVCExpander__T_1062, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1685_bits = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_1104_bits, ibuf_RVCExpander__T_1073_bits) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1685_rs1 = mux(ibuf_RVCExpander__T_1574, UInt<5>("h2"), ibuf_RVCExpander__T_381) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1691_bits = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1675_bits, ibuf_RVCExpander__T_1685_bits) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1691_rs1 = mux(ibuf_RVCExpander__T_1570, UInt<5>("h2"), ibuf_RVCExpander__T_1685_rs1) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1691_rs2 = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1645_rs2, ibuf_RVCExpander__T_1645_rs2) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1697_bits = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1661_bits, ibuf_RVCExpander__T_1691_bits) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1697_rd = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1661_rd, ibuf_RVCExpander__T_1591_rd) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1697_rs1 = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1661_rs1, ibuf_RVCExpander__T_1691_rs1) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1697_rs2 = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1661_rs2, ibuf_RVCExpander__T_1691_rs2) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1697_rs3 = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1661_rs3, ibuf_RVCExpander__T_1591_rs3) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1703_bits = mux(ibuf_RVCExpander__T_1562, ibuf_inst, ibuf_RVCExpander__T_1697_bits) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1703_rd = mux(ibuf_RVCExpander__T_1562, ibuf_RVCExpander__T_1627_rd, ibuf_RVCExpander__T_1697_rd) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1703_rs1 = mux(ibuf_RVCExpander__T_1562, ibuf_RVCExpander__T_1627_rs1, ibuf_RVCExpander__T_1697_rs1) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1703_rs2 = mux(ibuf_RVCExpander__T_1562, ibuf_RVCExpander__T_1627_rs2, ibuf_RVCExpander__T_1697_rs2) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1703_rs3 = mux(ibuf_RVCExpander__T_1562, ibuf_RVCExpander__T_1627_rs3, ibuf_RVCExpander__T_1697_rs3) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1725_bits = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_1033, ibuf_RVCExpander__T_936) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1725_rd = mux(ibuf_RVCExpander__T_1574, UInt<5>("h0"), ibuf_RVCExpander__T_66) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1725_rs1 = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_66, ibuf_RVCExpander__T_66) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1735_bits = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_839, ibuf_RVCExpander__T_722) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1735_rs2 = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_34, ibuf_RVCExpander__T_34) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1741_bits = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1725_bits, ibuf_RVCExpander__T_1735_bits) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1741_rd = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1725_rd, ibuf_RVCExpander__T_1725_rd) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1741_rs1 = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1725_rs1, ibuf_RVCExpander__T_1725_rs1) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1741_rs2 = mux(ibuf_RVCExpander__T_1570, UInt<5>("h0"), ibuf_RVCExpander__T_1735_rs2) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1755_bits = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_580_bits, ibuf_RVCExpander__T_459) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1755_rd = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_580_rd, ibuf_RVCExpander__T_381) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1755_rs1 = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_580_rd, UInt<5>("h0")) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1755_rs2 = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_580_rs2, ibuf_RVCExpander__T_34) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1755_rs3 = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_580_rs3, ibuf_RVCExpander__T_46) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1765_bits = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_426, ibuf_RVCExpander__T_388) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1771_bits = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1755_bits, ibuf_RVCExpander__T_1765_bits) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1771_rd = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1755_rd, ibuf_RVCExpander__T_1575_rd) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1771_rs1 = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1755_rs1, ibuf_RVCExpander__T_1575_rd) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1771_rs2 = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1755_rs2, ibuf_RVCExpander__T_1735_rs2) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1771_rs3 = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1755_rs3, ibuf_RVCExpander__T_1575_rs3) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1777_bits = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1741_bits, ibuf_RVCExpander__T_1771_bits) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1777_rd = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1741_rd, ibuf_RVCExpander__T_1771_rd) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1777_rs1 = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1741_rs1, ibuf_RVCExpander__T_1771_rs1) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1777_rs2 = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1741_rs2, ibuf_RVCExpander__T_1771_rs2) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1777_rs3 = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1591_rs3, ibuf_RVCExpander__T_1771_rs3) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_368_bits = pad(ibuf_RVCExpander__T_351, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_321_bits = pad(ibuf_RVCExpander__T_304, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1795_bits = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_368_bits, ibuf_RVCExpander__T_321_bits) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_270_bits = pad(ibuf_RVCExpander__T_253, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_223_bits = pad(ibuf_RVCExpander__T_206, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1805_bits = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_270_bits, ibuf_RVCExpander__T_223_bits) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1811_bits = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1795_bits, ibuf_RVCExpander__T_1805_bits) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1811_rd = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1735_rs2, ibuf_RVCExpander__T_1735_rs2) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_172_bits = pad(ibuf_RVCExpander__T_155, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_133_bits = pad(ibuf_RVCExpander__T_116, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1825_bits = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_172_bits, ibuf_RVCExpander__T_133_bits) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_92_bits = pad(ibuf_RVCExpander__T_75, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_53_bits = pad(ibuf_RVCExpander__T_38, 32) @[RVC.scala 21:19 22:14]
    node ibuf_RVCExpander__T_1835_bits = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_92_bits, ibuf_RVCExpander__T_53_bits) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1835_rs1 = mux(ibuf_RVCExpander__T_1574, ibuf_RVCExpander__T_66, UInt<5>("h2")) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1841_bits = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1825_bits, ibuf_RVCExpander__T_1835_bits) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1841_rs1 = mux(ibuf_RVCExpander__T_1570, ibuf_RVCExpander__T_1725_rs1, ibuf_RVCExpander__T_1835_rs1) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1847_bits = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1811_bits, ibuf_RVCExpander__T_1841_bits) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1847_rd = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1811_rd, ibuf_RVCExpander__T_1811_rd) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1847_rs1 = mux(ibuf_RVCExpander__T_1566, ibuf_RVCExpander__T_1741_rs1, ibuf_RVCExpander__T_1841_rs1) @[Package.scala 19:12]
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    node ibuf_RVCExpander__T_1853_bits = mux(ibuf_RVCExpander__T_1562, ibuf_RVCExpander__T_1777_bits, ibuf_RVCExpander__T_1847_bits) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1853_rd = mux(ibuf_RVCExpander__T_1562, ibuf_RVCExpander__T_1777_rd, ibuf_RVCExpander__T_1847_rd) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1853_rs1 = mux(ibuf_RVCExpander__T_1562, ibuf_RVCExpander__T_1777_rs1, ibuf_RVCExpander__T_1847_rs1) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1853_rs2 = mux(ibuf_RVCExpander__T_1562, ibuf_RVCExpander__T_1777_rs2, ibuf_RVCExpander__T_1847_rd) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1853_rs3 = mux(ibuf_RVCExpander__T_1562, ibuf_RVCExpander__T_1777_rs3, ibuf_RVCExpander__T_1627_rs3) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1859_bits = mux(ibuf_RVCExpander__T_1558, ibuf_RVCExpander__T_1703_bits, ibuf_RVCExpander__T_1853_bits) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1859_rd = mux(ibuf_RVCExpander__T_1558, ibuf_RVCExpander__T_1703_rd, ibuf_RVCExpander__T_1853_rd) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1859_rs1 = mux(ibuf_RVCExpander__T_1558, ibuf_RVCExpander__T_1703_rs1, ibuf_RVCExpander__T_1853_rs1) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1859_rs2 = mux(ibuf_RVCExpander__T_1558, ibuf_RVCExpander__T_1703_rs2, ibuf_RVCExpander__T_1853_rs2) @[Package.scala 19:12]
    node ibuf_RVCExpander__T_1859_rs3 = mux(ibuf_RVCExpander__T_1558, ibuf_RVCExpander__T_1703_rs3, ibuf_RVCExpander__T_1853_rs3) @[Package.scala 19:12]
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    reg ibuf_buf_pc : UInt<40>, const_clock with :
      reset => (UInt<1>("h0"), ibuf_buf_pc) @[IBuf.scala 36:16]
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    reg ibuf_buf_xcpt_if : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ibuf_buf_xcpt_if) @[IBuf.scala 36:16]
    reg ibuf_buf_replay : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ibuf_buf_replay) @[IBuf.scala 36:16]
    reg ibuf_ibufBTBHit : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ibuf_ibufBTBHit) @[IBuf.scala 37:23]
    reg ibuf_ibufBTBResp_taken : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ibuf_ibufBTBResp_taken) @[IBuf.scala 38:24]
    reg ibuf_ibufBTBResp_mask : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), ibuf_ibufBTBResp_mask) @[IBuf.scala 38:24]
    reg ibuf_ibufBTBResp_bridx : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ibuf_ibufBTBResp_bridx) @[IBuf.scala 38:24]
    reg ibuf_ibufBTBResp_target : UInt<39>, const_clock with :
      reset => (UInt<1>("h0"), ibuf_ibufBTBResp_target) @[IBuf.scala 38:24]
    reg ibuf_ibufBTBResp_entry : UInt<6>, const_clock with :
      reset => (UInt<1>("h0"), ibuf_ibufBTBResp_entry) @[IBuf.scala 38:24]
    reg ibuf_ibufBTBResp_bht_history : UInt<7>, const_clock with :
      reset => (UInt<1>("h0"), ibuf_ibufBTBResp_bht_history) @[IBuf.scala 38:24]
    reg ibuf_ibufBTBResp_bht_value : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), ibuf_ibufBTBResp_bht_value) @[IBuf.scala 38:24]
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    node ibuf__T_375 = and(io_imem_resp_bits_btb_valid, io_imem_resp_bits_btb_bits_taken) @[IBuf.scala 43:40]
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    node ibuf__T_377 = add(io_imem_resp_bits_btb_bits_bridx, UInt<1>("h1")) @[IBuf.scala 43:100]
    node ibuf__T_379 = mux(ibuf__T_375, ibuf__T_377, UInt<2>("h2")) @[IBuf.scala 43:16]
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    node ibuf__T_380 = sub(ibuf__T_379, _GEN_178) @[IBuf.scala 43:124]
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    node ibuf_nIC = tail(ibuf__T_380, 1) @[IBuf.scala 43:124]
    reg ex_reg_valid : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_valid) @[Rocket.scala 120:35]
    reg ex_ctrl_wxd : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_wxd) @[Rocket.scala 115:20]
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    node _T_2856 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h44")) @[Decode.scala 13:65]
    node _T_2858 = eq(_T_2856, UInt<32>("h0")) @[Decode.scala 13:121]
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    node _T_2860 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h4024")) @[Decode.scala 13:65]
    node _T_2862 = eq(_T_2860, UInt<32>("h20")) @[Decode.scala 13:121]
    node _T_2877 = or(_T_2858, _T_2862) @[Decode.scala 14:30]
    node _T_2864 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h38")) @[Decode.scala 13:65]
    node _T_2866 = eq(_T_2864, UInt<32>("h20")) @[Decode.scala 13:121]
    node _T_2878 = or(_T_2877, _T_2866) @[Decode.scala 14:30]
    node _T_2868 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h2050")) @[Decode.scala 13:65]
    node _T_2870 = eq(_T_2868, UInt<32>("h2000")) @[Decode.scala 13:121]
    node _T_2879 = or(_T_2878, _T_2870) @[Decode.scala 14:30]
    node _T_2872 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h90000034")) @[Decode.scala 13:65]
    node _T_2874 = eq(_T_2872, UInt<32>("h90000010")) @[Decode.scala 13:121]
    node id_ctrl_rxs1 = or(_T_2879, _T_2874) @[Decode.scala 14:30]
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    node _T_4232 = neq(ibuf_RVCExpander__T_1859_rs1, UInt<5>("h0")) @[Rocket.scala 479:55]
    node _T_4233 = and(id_ctrl_rxs1, _T_4232) @[Rocket.scala 479:42]
    reg ex_reg_inst : UInt<32>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_inst) @[Rocket.scala 130:24]
    node ex_waddr = bits(ex_reg_inst, 11, 7) @[Rocket.scala 235:29]
    node _T_4275 = eq(ibuf_RVCExpander__T_1859_rs1, ex_waddr) @[Rocket.scala 494:70]
    node _T_4276 = and(_T_4233, _T_4275) @[Rocket.scala 648:27]
    node _T_2835 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h64")) @[Decode.scala 13:65]
    node _T_2837 = eq(_T_2835, UInt<32>("h20")) @[Decode.scala 13:121]
    skip
    node _T_2839 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h34")) @[Decode.scala 13:65]
    node _T_2841 = eq(_T_2839, UInt<32>("h20")) @[Decode.scala 13:121]
    node _T_2852 = or(_T_2837, _T_2841) @[Decode.scala 14:30]
    node _T_2843 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h2048")) @[Decode.scala 13:65]
    node _T_2845 = eq(_T_2843, UInt<32>("h2008")) @[Decode.scala 13:121]
    node _T_2853 = or(_T_2852, _T_2845) @[Decode.scala 14:30]
    node _T_2847 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h42003024")) @[Decode.scala 13:65]
    node _T_2849 = eq(_T_2847, UInt<32>("h2000020")) @[Decode.scala 13:121]
    node id_ctrl_rxs2 = or(_T_2853, _T_2849) @[Decode.scala 14:30]
    skip
    skip
    skip
    node _T_4235 = neq(ibuf_RVCExpander__T_1859_rs2, UInt<5>("h0")) @[Rocket.scala 480:55]
    node _T_4236 = and(id_ctrl_rxs2, _T_4235) @[Rocket.scala 480:42]
    node _T_4277 = eq(ibuf_RVCExpander__T_1859_rs2, ex_waddr) @[Rocket.scala 494:70]
    node _T_4278 = and(_T_4236, _T_4277) @[Rocket.scala 648:27]
    node _T_4281 = or(_T_4276, _T_4278) @[Rocket.scala 648:50]
    skip
    node _T_3240 = eq(_T_2835, UInt<32>("h0")) @[Decode.scala 13:121]
    skip
    node _T_3242 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h50")) @[Decode.scala 13:65]
    node _T_3244 = eq(_T_3242, UInt<32>("h10")) @[Decode.scala 13:121]
    node _T_3267 = or(_T_3240, _T_3244) @[Decode.scala 14:30]
    node _T_3246 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h2024")) @[Decode.scala 13:65]
    node _T_3248 = eq(_T_3246, UInt<32>("h24")) @[Decode.scala 13:121]
    node _T_3268 = or(_T_3267, _T_3248) @[Decode.scala 14:30]
    node _T_3250 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h28")) @[Decode.scala 13:65]
    node _T_3252 = eq(_T_3250, UInt<32>("h28")) @[Decode.scala 13:121]
    node _T_3269 = or(_T_3268, _T_3252) @[Decode.scala 14:30]
    node _T_3254 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h1030")) @[Decode.scala 13:65]
    node _T_3256 = eq(_T_3254, UInt<32>("h1030")) @[Decode.scala 13:121]
    node _T_3270 = or(_T_3269, _T_3256) @[Decode.scala 14:30]
    node _T_3258 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h2030")) @[Decode.scala 13:65]
    node _T_3260 = eq(_T_3258, UInt<32>("h2030")) @[Decode.scala 13:121]
    node _T_3271 = or(_T_3270, _T_3260) @[Decode.scala 14:30]
    node _T_3262 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h90000010")) @[Decode.scala 13:65]
    node _T_3264 = eq(_T_3262, UInt<32>("h80000010")) @[Decode.scala 13:121]
    node id_ctrl_wxd = or(_T_3271, _T_3264) @[Decode.scala 14:30]
    skip
    skip
    skip
    node _T_4238 = neq(ibuf_RVCExpander__T_1859_rd, UInt<5>("h0")) @[Rocket.scala 481:55]
    node _T_4239 = and(id_ctrl_wxd, _T_4238) @[Rocket.scala 481:42]
    node _T_4279 = eq(ibuf_RVCExpander__T_1859_rd, ex_waddr) @[Rocket.scala 494:70]
    node _T_4280 = and(_T_4239, _T_4279) @[Rocket.scala 648:27]
    node _T_4282 = or(_T_4281, _T_4280) @[Rocket.scala 648:50]
    node data_hazard_ex = and(ex_ctrl_wxd, _T_4282) @[Rocket.scala 494:36]
    reg ex_ctrl_csr : UInt<3>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_csr) @[Rocket.scala 115:20]
    node _T_4270 = neq(ex_ctrl_csr, UInt<3>("h0")) @[Rocket.scala 493:38]
    reg ex_ctrl_jalr : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_jalr) @[Rocket.scala 115:20]
    node _T_4271 = or(_T_4270, ex_ctrl_jalr) @[Rocket.scala 493:48]
    reg ex_ctrl_mem : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_mem) @[Rocket.scala 115:20]
    node _T_4272 = or(_T_4271, ex_ctrl_mem) @[Rocket.scala 493:64]
    reg ex_ctrl_div : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_div) @[Rocket.scala 115:20]
    node _T_4273 = or(_T_4272, ex_ctrl_div) @[Rocket.scala 493:79]
    reg ex_ctrl_fp : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_fp) @[Rocket.scala 115:20]
    node ex_cannot_bypass = or(_T_4273, ex_ctrl_fp) @[Rocket.scala 493:94]
    skip
    skip
    node _T_4294 = and(data_hazard_ex, ex_cannot_bypass) @[Rocket.scala 496:54]
    reg ex_ctrl_wfd : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_wfd) @[Rocket.scala 115:20]
    skip
    node _T_4284 = and(io_fpu_dec_ren1, _T_4275) @[Rocket.scala 648:27]
    skip
    node _T_4286 = and(io_fpu_dec_ren2, _T_4277) @[Rocket.scala 648:27]
    node _T_4291 = or(_T_4284, _T_4286) @[Rocket.scala 648:50]
    skip
    skip
    node _T_4287 = eq(ibuf_RVCExpander__T_1859_rs3, ex_waddr) @[Rocket.scala 495:76]
    node _T_4288 = and(io_fpu_dec_ren3, _T_4287) @[Rocket.scala 648:27]
    node _T_4292 = or(_T_4291, _T_4288) @[Rocket.scala 648:50]
    skip
    node _T_4290 = and(io_fpu_dec_wen, _T_4279) @[Rocket.scala 648:27]
    node _T_4293 = or(_T_4292, _T_4290) @[Rocket.scala 648:50]
    node fp_data_hazard_ex = and(ex_ctrl_wfd, _T_4293) @[Rocket.scala 495:39]
    node _T_4295 = or(_T_4294, fp_data_hazard_ex) @[Rocket.scala 496:74]
    node id_ex_hazard = and(ex_reg_valid, _T_4295) @[Rocket.scala 496:35]
    reg mem_reg_valid : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_valid) @[Rocket.scala 133:36]
    reg mem_ctrl_wxd : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_ctrl_wxd) @[Rocket.scala 116:21]
    reg mem_reg_inst : UInt<32>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_inst) @[Rocket.scala 145:25]
    node mem_waddr = bits(mem_reg_inst, 11, 7) @[Rocket.scala 236:31]
    node _T_4303 = eq(ibuf_RVCExpander__T_1859_rs1, mem_waddr) @[Rocket.scala 503:72]
    node _T_4304 = and(_T_4233, _T_4303) @[Rocket.scala 648:27]
    node _T_4305 = eq(ibuf_RVCExpander__T_1859_rs2, mem_waddr) @[Rocket.scala 503:72]
    node _T_4306 = and(_T_4236, _T_4305) @[Rocket.scala 648:27]
    node _T_4309 = or(_T_4304, _T_4306) @[Rocket.scala 648:50]
    node _T_4307 = eq(ibuf_RVCExpander__T_1859_rd, mem_waddr) @[Rocket.scala 503:72]
    node _T_4308 = and(_T_4239, _T_4307) @[Rocket.scala 648:27]
    node _T_4310 = or(_T_4309, _T_4308) @[Rocket.scala 648:50]
    node data_hazard_mem = and(mem_ctrl_wxd, _T_4310) @[Rocket.scala 503:38]
    reg mem_ctrl_csr : UInt<3>, const_clock with :
      reset => (UInt<1>("h0"), mem_ctrl_csr) @[Rocket.scala 116:21]
    node _T_4298 = neq(mem_ctrl_csr, UInt<3>("h0")) @[Rocket.scala 502:40]
    reg mem_ctrl_mem : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_ctrl_mem) @[Rocket.scala 116:21]
    reg mem_reg_slow_bypass : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_slow_bypass) @[Rocket.scala 141:36]
    skip
    node _T_4299 = and(mem_ctrl_mem, mem_reg_slow_bypass) @[Rocket.scala 502:66]
    node _T_4300 = or(_T_4298, _T_4299) @[Rocket.scala 502:50]
    reg mem_ctrl_div : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_ctrl_div) @[Rocket.scala 116:21]
    node _T_4301 = or(_T_4300, mem_ctrl_div) @[Rocket.scala 502:84]
    reg mem_ctrl_fp : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_ctrl_fp) @[Rocket.scala 116:21]
    node mem_cannot_bypass = or(_T_4301, mem_ctrl_fp) @[Rocket.scala 502:100]
    skip
    skip
    node _T_4322 = and(data_hazard_mem, mem_cannot_bypass) @[Rocket.scala 505:57]
    reg mem_ctrl_wfd : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_ctrl_wfd) @[Rocket.scala 116:21]
    skip
    node _T_4312 = and(io_fpu_dec_ren1, _T_4303) @[Rocket.scala 648:27]
    skip
    node _T_4314 = and(io_fpu_dec_ren2, _T_4305) @[Rocket.scala 648:27]
    node _T_4319 = or(_T_4312, _T_4314) @[Rocket.scala 648:50]
    node _T_4315 = eq(ibuf_RVCExpander__T_1859_rs3, mem_waddr) @[Rocket.scala 504:78]
    node _T_4316 = and(io_fpu_dec_ren3, _T_4315) @[Rocket.scala 648:27]
    node _T_4320 = or(_T_4319, _T_4316) @[Rocket.scala 648:50]
    skip
    node _T_4318 = and(io_fpu_dec_wen, _T_4307) @[Rocket.scala 648:27]
    node _T_4321 = or(_T_4320, _T_4318) @[Rocket.scala 648:50]
    node fp_data_hazard_mem = and(mem_ctrl_wfd, _T_4321) @[Rocket.scala 504:41]
    node _T_4323 = or(_T_4322, fp_data_hazard_mem) @[Rocket.scala 505:78]
    node id_mem_hazard = and(mem_reg_valid, _T_4323) @[Rocket.scala 505:37]
    node _T_4405 = or(id_ex_hazard, id_mem_hazard) @[Rocket.scala 528:18]
    reg wb_reg_valid : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), wb_reg_valid) @[Rocket.scala 150:35]
    reg wb_ctrl_wxd : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), wb_ctrl_wxd) @[Rocket.scala 117:20]
    reg wb_reg_inst : UInt<32>, const_clock with :
      reset => (UInt<1>("h0"), wb_reg_inst) @[Rocket.scala 155:24]
    node wb_waddr = bits(wb_reg_inst, 11, 7) @[Rocket.scala 237:29]
    node _T_4326 = eq(ibuf_RVCExpander__T_1859_rs1, wb_waddr) @[Rocket.scala 509:70]
    node _T_4327 = and(_T_4233, _T_4326) @[Rocket.scala 648:27]
    node _T_4328 = eq(ibuf_RVCExpander__T_1859_rs2, wb_waddr) @[Rocket.scala 509:70]
    node _T_4329 = and(_T_4236, _T_4328) @[Rocket.scala 648:27]
    node _T_4332 = or(_T_4327, _T_4329) @[Rocket.scala 648:50]
    node _T_4330 = eq(ibuf_RVCExpander__T_1859_rd, wb_waddr) @[Rocket.scala 509:70]
    node _T_4331 = and(_T_4239, _T_4330) @[Rocket.scala 648:27]
    node _T_4333 = or(_T_4332, _T_4331) @[Rocket.scala 648:50]
    node data_hazard_wb = and(wb_ctrl_wxd, _T_4333) @[Rocket.scala 509:36]
    reg wb_ctrl_div : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), wb_ctrl_div) @[Rocket.scala 117:20]
    reg wb_ctrl_mem : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), wb_ctrl_mem) @[Rocket.scala 117:20]
    node _T_3783 = not(io_dmem_resp_valid) @[Rocket.scala 324:39]
    node wb_dcache_miss = and(wb_ctrl_mem, _T_3783) @[Rocket.scala 324:36]
    node wb_set_sboard = or(wb_ctrl_div, wb_dcache_miss) @[Rocket.scala 415:35]
    skip
    skip
    node _T_4345 = and(data_hazard_wb, wb_set_sboard) @[Rocket.scala 511:54]
    reg wb_ctrl_wfd : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), wb_ctrl_wfd) @[Rocket.scala 117:20]
    skip
    node _T_4335 = and(io_fpu_dec_ren1, _T_4326) @[Rocket.scala 648:27]
    skip
    node _T_4337 = and(io_fpu_dec_ren2, _T_4328) @[Rocket.scala 648:27]
    node _T_4342 = or(_T_4335, _T_4337) @[Rocket.scala 648:50]
    node _T_4338 = eq(ibuf_RVCExpander__T_1859_rs3, wb_waddr) @[Rocket.scala 510:76]
    node _T_4339 = and(io_fpu_dec_ren3, _T_4338) @[Rocket.scala 648:27]
    node _T_4343 = or(_T_4342, _T_4339) @[Rocket.scala 648:50]
    skip
    node _T_4341 = and(io_fpu_dec_wen, _T_4330) @[Rocket.scala 648:27]
    node _T_4344 = or(_T_4343, _T_4341) @[Rocket.scala 648:50]
    node fp_data_hazard_wb = and(wb_ctrl_wfd, _T_4344) @[Rocket.scala 510:39]
    node _T_4346 = or(_T_4345, fp_data_hazard_wb) @[Rocket.scala 511:71]
    node id_wb_hazard = and(wb_reg_valid, _T_4346) @[Rocket.scala 511:35]
    node _T_4406 = or(_T_4405, id_wb_hazard) @[Rocket.scala 528:35]
    reg _T_4241 : UInt<32>, const_clock with :
      reset => (UInt<1>("h0"), _T_4241) @[Rocket.scala 668:25]
    node _T_4242 = shr(_T_4241, 1) @[Rocket.scala 669:35]
    node _T_4243 = shl(_T_4242, 1) @[Rocket.scala 669:40]
    node _T_4252 = dshr(_T_4243, ibuf_RVCExpander__T_1859_rs1) @[Rocket.scala 665:35]
    node _T_4253 = bits(_T_4252, 0, 0) @[Rocket.scala 665:35]
    node _T_4254 = and(_T_4233, _T_4253) @[Rocket.scala 648:27]
    node _T_4255 = dshr(_T_4243, ibuf_RVCExpander__T_1859_rs2) @[Rocket.scala 665:35]
    node _T_4256 = bits(_T_4255, 0, 0) @[Rocket.scala 665:35]
    node _T_4257 = and(_T_4236, _T_4256) @[Rocket.scala 648:27]
    node _T_4261 = or(_T_4254, _T_4257) @[Rocket.scala 648:50]
    node _T_4258 = dshr(_T_4243, ibuf_RVCExpander__T_1859_rd) @[Rocket.scala 665:35]
    node _T_4259 = bits(_T_4258, 0, 0) @[Rocket.scala 665:35]
    node _T_4260 = and(_T_4239, _T_4259) @[Rocket.scala 648:27]
    node id_sboard_hazard = or(_T_4261, _T_4260) @[Rocket.scala 648:50]
    node _T_4407 = or(_T_4406, id_sboard_hazard) @[Rocket.scala 528:51]
    node _T_2805 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h5c")) @[Decode.scala 13:65]
    node _T_2807 = eq(_T_2805, UInt<32>("h4")) @[Decode.scala 13:121]
    skip
    node _T_2809 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h60")) @[Decode.scala 13:65]
    node _T_2811 = eq(_T_2809, UInt<32>("h40")) @[Decode.scala 13:121]
    node id_ctrl_fp = or(_T_2807, _T_2811) @[Decode.scala 14:30]
    skip
    node _T_3286 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h3070")) @[Decode.scala 13:65]
    node _T_3288 = eq(_T_3286, UInt<32>("h70")) @[Decode.scala 13:121]
    skip
    node _T_3280 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h2070")) @[Decode.scala 13:65]
    node _T_3282 = eq(_T_3280, UInt<32>("h2070")) @[Decode.scala 13:121]
    skip
    node _T_3291 = cat(_T_3288, _T_3282) @[Cat.scala 30:58]
    node _T_3274 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h1070")) @[Decode.scala 13:65]
    node _T_3276 = eq(_T_3274, UInt<32>("h1070")) @[Decode.scala 13:121]
    skip
    node id_ctrl_csr = cat(_T_3291, _T_3276) @[Cat.scala 30:58]
    skip
    node _T_3450 = eq(id_ctrl_csr, UInt<3>("h2")) @[Package.scala 7:47]
    node _T_3451 = eq(id_ctrl_csr, UInt<3>("h3")) @[Package.scala 7:47]
    node _T_3453 = or(_T_3450, _T_3451) @[Package.scala 7:62]
    node _T_3452 = eq(id_ctrl_csr, UInt<3>("h1")) @[Package.scala 7:47]
    node id_csr_en = or(_T_3453, _T_3452) @[Package.scala 7:62]
    node _T_4375 = not(io_fpu_fcsr_rdy) @[Rocket.scala 519:18]
    node _T_4376 = and(id_csr_en, _T_4375) @[Rocket.scala 519:15]
    reg _T_4348 : UInt<32>, const_clock with :
      reset => (UInt<1>("h0"), _T_4348) @[Rocket.scala 668:25]
    node _T_4377 = dshr(_T_4348, ibuf_RVCExpander__T_1859_rs1) @[Rocket.scala 665:35]
    node _T_4378 = bits(_T_4377, 0, 0) @[Rocket.scala 665:35]
    node _T_4379 = and(io_fpu_dec_ren1, _T_4378) @[Rocket.scala 648:27]
    node _T_4380 = dshr(_T_4348, ibuf_RVCExpander__T_1859_rs2) @[Rocket.scala 665:35]
    node _T_4381 = bits(_T_4380, 0, 0) @[Rocket.scala 665:35]
    node _T_4382 = and(io_fpu_dec_ren2, _T_4381) @[Rocket.scala 648:27]
    node _T_4389 = or(_T_4379, _T_4382) @[Rocket.scala 648:50]
    node _T_4383 = dshr(_T_4348, ibuf_RVCExpander__T_1859_rs3) @[Rocket.scala 665:35]
    node _T_4384 = bits(_T_4383, 0, 0) @[Rocket.scala 665:35]
    node _T_4385 = and(io_fpu_dec_ren3, _T_4384) @[Rocket.scala 648:27]
    node _T_4390 = or(_T_4389, _T_4385) @[Rocket.scala 648:50]
    node _T_4386 = dshr(_T_4348, ibuf_RVCExpander__T_1859_rd) @[Rocket.scala 665:35]
    node _T_4387 = bits(_T_4386, 0, 0) @[Rocket.scala 665:35]
    node _T_4388 = and(io_fpu_dec_wen, _T_4387) @[Rocket.scala 648:27]
    node _T_4391 = or(_T_4390, _T_4388) @[Rocket.scala 648:50]
    node id_stall_fpu = or(_T_4376, _T_4391) @[Rocket.scala 519:35]
    node _T_4408 = and(id_ctrl_fp, id_stall_fpu) @[Rocket.scala 529:16]
    node _T_4409 = or(_T_4407, _T_4408) @[Rocket.scala 528:71]
    node _T_3083 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h405f")) @[Decode.scala 13:65]
    node _T_3085 = eq(_T_3083, UInt<32>("h3")) @[Decode.scala 13:121]
    skip
    node _T_2603 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h207f")) @[Decode.scala 13:65]
    node _T_2605 = eq(_T_2603, UInt<32>("h3")) @[Decode.scala 13:121]
    node _T_3096 = or(_T_3085, _T_2605) @[Decode.scala 14:30]
    node _T_3087 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h107f")) @[Decode.scala 13:65]
    node _T_3089 = eq(_T_3087, UInt<32>("h3")) @[Decode.scala 13:121]
    node _T_3097 = or(_T_3096, _T_3089) @[Decode.scala 14:30]
    node _T_3091 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h707f")) @[Decode.scala 13:65]
    node _T_3093 = eq(_T_3091, UInt<32>("h100f")) @[Decode.scala 13:121]
    node _T_3098 = or(_T_3097, _T_3093) @[Decode.scala 14:30]
    node _T_2659 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h605b")) @[Decode.scala 13:65]
    node _T_2661 = eq(_T_2659, UInt<32>("h2003")) @[Decode.scala 13:121]
    node _T_3099 = or(_T_3098, _T_2661) @[Decode.scala 14:30]
    node _T_2667 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h1800607f")) @[Decode.scala 13:65]
    node _T_2669 = eq(_T_2667, UInt<32>("h202f")) @[Decode.scala 13:121]
    node _T_3100 = or(_T_3099, _T_2669) @[Decode.scala 14:30]
    node _T_2691 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("he800607f")) @[Decode.scala 13:65]
    node _T_2693 = eq(_T_2691, UInt<32>("h800202f")) @[Decode.scala 13:121]
    node _T_3101 = or(_T_3100, _T_2693) @[Decode.scala 14:30]
    node _T_2695 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hf9f0607f")) @[Decode.scala 13:65]
    node _T_2697 = eq(_T_2695, UInt<32>("h1000202f")) @[Decode.scala 13:121]
    node id_ctrl_mem = or(_T_3101, _T_2697) @[Decode.scala 14:30]
    skip
    reg dcache_blocked : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), dcache_blocked) @[Rocket.scala 522:27]
    node _T_4410 = and(id_ctrl_mem, dcache_blocked) @[Rocket.scala 530:17]
    node _T_4411 = or(_T_4409, _T_4410) @[Rocket.scala 529:32]
    skip
    skip
    skip
    skip
    node _T_3232 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h2000074")) @[Decode.scala 13:65]
    node id_ctrl_div = eq(_T_3232, UInt<32>("h2000030")) @[Decode.scala 13:121]
    skip
    skip
    skip
    reg div_state : UInt<3>, const_clock with :
      reset => (UInt<1>("h0"), div_state) @[Multiplier.scala 45:18]
    node div__T_709 = eq(div_state, UInt<3>("h0")) @[Multiplier.scala 167:25]
    skip
    node div__T_708 = eq(div_state, UInt<3>("h5")) @[Multiplier.scala 166:26]
    skip
    node wb_wxd = and(wb_reg_valid, wb_ctrl_wxd) @[Rocket.scala 414:29]
    node _T_4415 = not(wb_wxd) @[Rocket.scala 532:65]
    node _T_4416 = and(div__T_708, _T_4415) @[Rocket.scala 532:62]
    node _T_4417 = or(div__T_709, _T_4416) @[Rocket.scala 532:40]
    node _T_4419 = not(_T_4417) @[Rocket.scala 532:21]
    node div_io_req_valid = and(ex_reg_valid, ex_ctrl_div) @[Rocket.scala 269:36]
    skip
    node _T_4420 = or(_T_4419, div_io_req_valid) @[Rocket.scala 532:75]
    node _T_4421 = and(id_ctrl_div, _T_4420) @[Rocket.scala 532:17]
    node _T_4422 = or(_T_4411, _T_4421) @[Rocket.scala 531:34]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    node _T_3300 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h3058")) @[Decode.scala 13:65]
    node id_ctrl_fence = eq(_T_3300, UInt<32>("h8")) @[Decode.scala 13:121]
    skip

    skip
    node _T_3503 = not(io_dmem_ordered) @[Rocket.scala 207:21]
    node id_mem_busy = or(_T_3503, io_dmem_req_valid) @[Rocket.scala 207:38]
    node _T_3306 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h6048")) @[Decode.scala 13:65]
    node id_ctrl_amo = eq(_T_3306, UInt<32>("h2008")) @[Decode.scala 13:121]
    skip
    skip
    node id_amo_aq = bits(ibuf_RVCExpander__T_1859_bits, 26, 26) @[Rocket.scala 204:29]
    node _T_3514 = and(id_ctrl_amo, id_amo_aq) @[Rocket.scala 213:33]
    skip
    node id_ctrl_fence_i = eq(_T_3300, UInt<32>("h1008")) @[Decode.scala 13:121]
    skip
    skip
    node _T_3515 = or(_T_3514, id_ctrl_fence_i) @[Rocket.scala 213:46]
    reg id_reg_fence : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), id_reg_fence) @[Rocket.scala 178:25]
    skip
    node _T_3517 = and(id_reg_fence, id_ctrl_mem) @[Rocket.scala 213:81]
    node _T_3518 = or(_T_3515, _T_3517) @[Rocket.scala 213:65]
    node id_do_fence = and(id_mem_busy, _T_3518) @[Rocket.scala 213:17]
    skip
    node _T_4423 = or(_T_4422, id_do_fence) @[Rocket.scala 532:96]
    skip
    reg csr_reg_wfi : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_wfi) @[CSR.scala 264:20]
    skip
    node ctrl_stalld = or(_T_4423, csr_reg_wfi) @[Rocket.scala 533:17]
    node _T_4443 = not(ctrl_stalld) @[Rocket.scala 547:28]
    reg csr_reg_dcsr_debugint : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_dcsr_debugint) @[CSR.scala 205:21]
    skip
    reg csr_reg_debug : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_debug) @[CSR.scala 232:22]
    node csr__T_1207 = not(csr_reg_debug) @[CSR.scala 291:50]
    node csr__T_1208 = and(csr_reg_dcsr_debugint, csr__T_1207) @[CSR.scala 291:47]
    reg csr_reg_mstatus_prv : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_prv) @[CSR.scala 197:24]
    node csr__T_983 = leq(csr_reg_mstatus_prv, UInt<2>("h1")) @[CSR.scala 281:42]
    node csr__T_985 = eq(csr_reg_mstatus_prv, UInt<2>("h3")) @[CSR.scala 281:71]
    reg csr_reg_mstatus_mie : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_mie) @[CSR.scala 197:24]
    node csr__T_986 = and(csr__T_985, csr_reg_mstatus_mie) @[CSR.scala 281:81]
    node csr__T_987 = or(csr__T_983, csr__T_986) @[CSR.scala 281:51]
    skip
    skip
    reg csr_reg_mip_meip : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mip_meip) @[CSR.scala 244:20]
    skip
    node csr__T_978 = cat(io_rocc_interrupt, csr_reg_mip_meip) @[CSR.scala 278:22]
    skip
    skip
    reg csr_reg_mip_seip : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mip_seip) @[CSR.scala 244:20]
    skip
    node csr__T_977 = cat(UInt<1>("h0"), csr_reg_mip_seip) @[CSR.scala 278:22]
    node csr__T_979 = cat(csr__T_978, csr__T_977) @[CSR.scala 278:22]
    skip
    skip
    reg csr_reg_mip_mtip : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mip_mtip) @[CSR.scala 244:20]
    skip
    node csr__T_975 = cat(UInt<1>("h0"), csr_reg_mip_mtip) @[CSR.scala 278:22]
    skip
    skip
    node csr__T_976 = cat(csr__T_975, UInt<1>("h0")) @[CSR.scala 278:22]
    node csr__T_980 = cat(csr__T_979, csr__T_976) @[CSR.scala 278:22]
    reg csr_reg_mip_stip : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mip_stip) @[CSR.scala 244:20]
    skip
    skip
    skip
    node csr__T_972 = cat(csr_reg_mip_stip, UInt<1>("h0")) @[CSR.scala 278:22]
    reg csr_reg_mip_msip : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mip_msip) @[CSR.scala 244:20]
    skip
    node csr__T_973 = cat(csr__T_972, csr_reg_mip_msip) @[CSR.scala 278:22]
    skip
    skip
    reg csr_reg_mip_ssip : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mip_ssip) @[CSR.scala 244:20]
    skip
    node csr__T_970 = cat(UInt<1>("h0"), csr_reg_mip_ssip) @[CSR.scala 278:22]
    skip
    skip
    node csr__T_971 = cat(csr__T_970, UInt<1>("h0")) @[CSR.scala 278:22]
    node csr__T_974 = cat(csr__T_973, csr__T_971) @[CSR.scala 278:22]
    node csr__T_981 = cat(csr__T_980, csr__T_974) @[CSR.scala 278:22]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    node csr_read_mip = and(csr__T_981, UInt<13>("haaa")) @[CSR.scala 278:29]
    reg csr_reg_mie : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mie) @[CSR.scala 241:20]
    node _GEN_182 = pad(csr_read_mip, 64) @[CSR.scala 280:37]
    node csr_pending_interrupts = and(_GEN_182, csr_reg_mie) @[CSR.scala 280:37]
    reg csr_reg_mideleg : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mideleg) @[CSR.scala 242:24]
    node csr__T_988 = not(csr_reg_mideleg) @[CSR.scala 281:123]
    node csr__T_989 = and(csr_pending_interrupts, csr__T_988) @[CSR.scala 281:121]
    node csr_m_interrupts = mux(csr__T_987, csr__T_989, UInt<64>("h0")) @[CSR.scala 281:25]
    node csr__T_992 = eq(csr_m_interrupts, UInt<64>("h0")) @[CSR.scala 282:39]
    node csr__T_994 = lt(csr_reg_mstatus_prv, UInt<2>("h1")) @[CSR.scala 282:65]
    node csr__T_996 = eq(csr_reg_mstatus_prv, UInt<2>("h1")) @[CSR.scala 282:93]
    reg csr_reg_mstatus_sie : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_sie) @[CSR.scala 197:24]
    node csr__T_997 = and(csr__T_996, csr_reg_mstatus_sie) @[CSR.scala 282:103]
    node csr__T_998 = or(csr__T_994, csr__T_997) @[CSR.scala 282:73]
    node csr__T_999 = and(csr__T_992, csr__T_998) @[CSR.scala 282:45]
    node csr__T_1000 = and(csr_pending_interrupts, csr_reg_mideleg) @[CSR.scala 282:144]
    node csr_s_interrupts = mux(csr__T_999, csr__T_1000, UInt<64>("h0")) @[CSR.scala 282:25]
    node csr_all_interrupts = or(csr_m_interrupts, csr_s_interrupts) @[CSR.scala 283:37]
    node csr__T_1196 = neq(csr_all_interrupts, UInt<64>("h0")) @[CSR.scala 286:34]
    skip
    node csr__T_1199 = and(csr__T_1196, csr__T_1207) @[CSR.scala 286:38]
    reg csr_reg_dcsr_step : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_dcsr_step) @[CSR.scala 205:21]
    skip
    node csr__T_2334 = and(csr_reg_dcsr_step, csr__T_1207) @[CSR.scala 451:34]
    skip
    node csr__T_1201 = not(csr__T_2334) @[CSR.scala 286:55]
    node csr__T_1202 = and(csr__T_1199, csr__T_1201) @[CSR.scala 286:52]
    reg csr_reg_singleStepped : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_singleStepped) @[CSR.scala 236:30]
    node csr__T_1203 = or(csr__T_1202, csr_reg_singleStepped) @[CSR.scala 286:70]
    node csr__GEN_2 = or(csr__T_1208, csr__T_1203) @[CSR.scala 286:16 291:62 292:18]
    skip
    node ibuf_io_inst_0_ready = or(_T_4443, csr__GEN_2) @[Rocket.scala 547:41]
    skip
    skip
    node ibuf__T_385 = mux(io_imem_resp_valid, ibuf_nIC, UInt<2>("h0")) @[IBuf.scala 45:19]
    skip
    node ibuf__T_386 = add(ibuf__T_385, _GEN_177) @[IBuf.scala 45:49]
    node ibuf_nValid = tail(ibuf__T_386, 1) @[IBuf.scala 45:49]
    node ibuf__T_456 = dshl(UInt<1>("h1"), ibuf_nValid) @[OneHot.scala 47:11]
    node ibuf__T_458 = sub(ibuf__T_456, UInt<4>("h1")) @[IBuf.scala 79:33]
    skip
    node ibuf__T_460 = tail(ibuf__T_458, 1) @[IBuf.scala 79:33]
    node ibuf_valid = bits(ibuf__T_460, 1, 0) @[IBuf.scala 79:37]
    skip
    node ibuf__T_529 = bits(ibuf_valid, 0, 0) @[IBuf.scala 100:32]
    skip
    skip
    skip
    node _GEN_184 = shr(ibuf_valid, 1) @[IBuf.scala 100:59]
    node ibuf__T_533 = pad(_GEN_184, 2) @[IBuf.scala 100:59]
    node ibuf__T_534 = bits(ibuf__T_533, 0, 0) @[IBuf.scala 100:59]
    node ibuf__T_535 = or(ibuf_RVCExpander__T_14, ibuf__T_534) @[IBuf.scala 100:51]
    node ibuf__T_462 = dshl(UInt<1>("h1"), ibuf_nBufValid) @[OneHot.scala 47:11]
    node ibuf__T_464 = sub(ibuf__T_462, UInt<2>("h1")) @[IBuf.scala 80:37]
    skip
    node ibuf_bufMask = tail(ibuf__T_464, 1) @[IBuf.scala 80:37]
    node ibuf__T_467 = mux(ibuf_buf_xcpt_if, ibuf_bufMask, UInt<2>("h0")) @[IBuf.scala 81:29]
    skip
    node ibuf__T_468 = not(ibuf_bufMask) @[IBuf.scala 81:89]
    node ibuf__T_470 = mux(io_imem_resp_bits_xcpt_if, ibuf__T_468, UInt<2>("h0")) @[IBuf.scala 81:66]
    node ibuf__T_471 = or(ibuf__T_467, ibuf__T_470) @[IBuf.scala 81:61]
    node ibuf_xcpt_if = and(ibuf_valid, ibuf__T_471) @[IBuf.scala 81:23]
    skip
    skip
    node _GEN_185 = shr(ibuf_xcpt_if, 1) @[IBuf.scala 100:75]
    node ibuf__T_539 = pad(_GEN_185, 2) @[IBuf.scala 100:75]
    node ibuf__T_540 = bits(ibuf__T_539, 0, 0) @[IBuf.scala 100:75]
    node ibuf__T_541 = or(ibuf__T_535, ibuf__T_540) @[IBuf.scala 100:65]
    node ibuf__T_473 = mux(ibuf_buf_replay, ibuf_bufMask, UInt<2>("h0")) @[IBuf.scala 82:31]
    skip
    skip
    node ibuf__T_476 = mux(io_imem_resp_bits_replay, ibuf__T_468, UInt<2>("h0")) @[IBuf.scala 82:67]
    node ibuf__T_477 = or(ibuf__T_473, ibuf__T_476) @[IBuf.scala 82:62]
    node ibuf_ic_replay = and(ibuf_valid, ibuf__T_477) @[IBuf.scala 82:25]
    skip
    node ibuf__T_515 = bits(ibuf_ic_replay, 0, 0) @[IBuf.scala 99:29]
    node ibuf__T_517 = not(ibuf_RVCExpander__T_14) @[IBuf.scala 99:37]
    node ibuf__T_479 = dshl(UInt<1>("h1"), ibuf_ibufBTBResp_bridx) @[OneHot.scala 47:11]
    node ibuf_ibufBTBHitMask = mux(ibuf_ibufBTBHit, ibuf__T_479, UInt<2>("h0")) @[IBuf.scala 83:27]
    node ibuf__T_495 = and(ibuf_ibufBTBHitMask, ibuf_bufMask) @[IBuf.scala 86:35]
    node ibuf__T_488 = add(io_imem_resp_bits_btb_bits_bridx, ibuf_nBufValid) @[IBuf.scala 85:87]
    skip
    node ibuf__T_489 = sub(ibuf__T_488, _GEN_178) @[IBuf.scala 85:100]
    skip
    node ibuf__T_491 = tail(ibuf__T_489, 1) @[IBuf.scala 85:100]
    node ibuf__T_493 = dshl(UInt<1>("h1"), ibuf__T_491) @[OneHot.scala 47:11]
    node ibuf_icBTBHitMask = mux(io_imem_resp_bits_btb_valid, ibuf__T_493, UInt<4>("h0")) @[IBuf.scala 85:25]
    skip
    node _GEN_187 = pad(ibuf__T_468, 4) @[IBuf.scala 86:60]
    node ibuf__T_497 = and(ibuf_icBTBHitMask, _GEN_187) @[IBuf.scala 86:60]
    node _GEN_188 = pad(ibuf__T_495, 4) @[IBuf.scala 86:45]
    node ibuf_btbHitMask = or(_GEN_188, ibuf__T_497) @[IBuf.scala 86:45]
    skip
    node ibuf__T_519 = bits(ibuf_btbHitMask, 0, 0) @[IBuf.scala 99:63]
    skip
    skip
    node _GEN_189 = shr(ibuf_ic_replay, 1) @[IBuf.scala 99:79]
    node ibuf__T_523 = pad(_GEN_189, 2) @[IBuf.scala 99:79]
    node ibuf__T_524 = bits(ibuf__T_523, 0, 0) @[IBuf.scala 99:79]
    node ibuf__T_525 = or(ibuf__T_519, ibuf__T_524) @[IBuf.scala 99:67]
    node ibuf__T_526 = and(ibuf__T_517, ibuf__T_525) @[IBuf.scala 99:49]
    node ibuf__T_527 = or(ibuf__T_515, ibuf__T_526) @[IBuf.scala 99:33]
    node ibuf__T_542 = or(ibuf__T_541, ibuf__T_527) @[IBuf.scala 100:81]
    node ibuf__T_543 = and(ibuf__T_529, ibuf__T_542) @[IBuf.scala 100:36]
    skip
    node ibuf__T_565 = and(ibuf_io_inst_0_ready, ibuf__T_543) @[Decoupled.scala 30:37]
    skip
    skip
    skip
    skip
    node ibuf__T_572 = mux(ibuf_RVCExpander__T_14, UInt<2>("h1"), UInt<2>("h2")) @[IBuf.scala 107:47]
    node ibuf__GEN_30 = mux(ibuf__T_565, ibuf__T_572, UInt<2>("h0")) @[IBuf.scala 107:{32,41}]
    skip
    skip
    node ibuf__T_382 = sub(ibuf__GEN_30, _GEN_177) @[IBuf.scala 44:25]
    skip
    node ibuf_nICReady = tail(ibuf__T_382, 1) @[IBuf.scala 44:25]
    skip
    node ibuf__T_387 = geq(ibuf__GEN_30, _GEN_177) @[IBuf.scala 46:27]
    node ibuf__T_388 = geq(ibuf_nICReady, ibuf_nIC) @[IBuf.scala 46:53]
    node ibuf__T_390 = sub(ibuf_nIC, ibuf_nICReady) @[IBuf.scala 46:72]
    skip
    node ibuf__T_392 = tail(ibuf__T_390, 1) @[IBuf.scala 46:72]
    node ibuf__T_393 = geq(UInt<2>("h1"), ibuf__T_392) @[IBuf.scala 46:65]
    node ibuf__T_394 = or(ibuf__T_388, ibuf__T_393) @[IBuf.scala 46:60]
    skip
    skip
    skip
    skip
    node ibuf__T_398 = sub(_GEN_177, ibuf__GEN_30) @[IBuf.scala 49:62]
    skip
    node ibuf__T_400 = tail(ibuf__T_398, 1) @[IBuf.scala 49:62]
    node ibuf__T_401 = mux(ibuf__T_387, UInt<2>("h0"), ibuf__T_400) @[IBuf.scala 49:21]
    skip
    skip
    node ibuf__T_403 = and(io_imem_resp_valid, ibuf__T_387) @[IBuf.scala 56:25]
    node ibuf__T_404 = lt(ibuf_nICReady, ibuf_nIC) @[IBuf.scala 56:60]
    node ibuf__T_405 = and(ibuf__T_403, ibuf__T_404) @[IBuf.scala 56:48]
    skip
    skip
    skip
    skip
    node ibuf__T_411 = and(ibuf__T_405, ibuf__T_393) @[IBuf.scala 56:66]
    skip
    node ibuf__T_412 = add(_GEN_178, ibuf_nICReady) @[IBuf.scala 57:30]
    node ibuf__T_413 = tail(ibuf__T_412, 1) @[IBuf.scala 57:30]
    skip
    skip
    skip
    node ibuf__T_417 = shr(io_imem_resp_bits_data, 16) @[IBuf.scala 133:58]
    node ibuf__T_418 = cat(ibuf__T_417, ibuf__T_417) @[Cat.scala 30:58]
    node ibuf__T_419 = cat(ibuf__T_418, io_imem_resp_bits_data) @[Cat.scala 30:58]
    node ibuf__T_420 = shl(ibuf__T_413, 4) @[IBuf.scala 134:19]
    node ibuf__T_421 = dshr(ibuf__T_419, ibuf__T_420) @[IBuf.scala 134:10]
    node ibuf__T_422 = bits(ibuf__T_421, 15, 0) @[IBuf.scala 60:59]
    skip
    node ibuf__T_424 = and(io_imem_resp_bits_pc, UInt<40>("hfffffffffc")) @[IBuf.scala 61:33]
    node ibuf__T_425 = shl(ibuf_nICReady, 1) @[IBuf.scala 61:78]
    node _GEN_196 = pad(ibuf__T_425, 40) @[IBuf.scala 61:66]
    node ibuf__T_426 = add(io_imem_resp_bits_pc, _GEN_196) @[IBuf.scala 61:66]
    node ibuf__T_427 = tail(ibuf__T_426, 1) @[IBuf.scala 61:66]
    node ibuf__T_428 = and(ibuf__T_427, UInt<40>("h3")) @[IBuf.scala 61:107]
    node ibuf__T_429 = or(ibuf__T_424, ibuf__T_428) @[IBuf.scala 61:47]
    node _GEN_197 = pad(io_imem_resp_bits_btb_bits_bridx, 2) @[IBuf.scala 65:58]
    node ibuf__T_430 = add(_GEN_197, ibuf_nICReady) @[IBuf.scala 65:58]
    node ibuf__T_431 = tail(ibuf__T_430, 1) @[IBuf.scala 65:58]
    node ibuf__GEN_0 = mux(io_imem_resp_bits_btb_valid, io_imem_resp_bits_btb_bits_taken, ibuf_ibufBTBResp_taken) @[IBuf.scala 63:37 64:21 38:24]
    skip
    node ibuf__GEN_1 = mux(io_imem_resp_bits_btb_valid, io_imem_resp_bits_btb_bits_mask, ibuf_ibufBTBResp_mask) @[IBuf.scala 63:37 64:21 38:24]
    node ibuf__GEN_2 = mux(io_imem_resp_bits_btb_valid, ibuf__T_431, pad(ibuf_ibufBTBResp_bridx, 2)) @[IBuf.scala 38:24 63:37 65:27]
    skip
    node ibuf__GEN_3 = mux(io_imem_resp_bits_btb_valid, io_imem_resp_bits_btb_bits_target, ibuf_ibufBTBResp_target) @[IBuf.scala 63:37 64:21 38:24]
    skip
    node ibuf__GEN_4 = mux(io_imem_resp_bits_btb_valid, io_imem_resp_bits_btb_bits_entry, ibuf_ibufBTBResp_entry) @[IBuf.scala 63:37 64:21 38:24]
    skip
    node ibuf__GEN_5 = mux(io_imem_resp_bits_btb_valid, io_imem_resp_bits_btb_bits_bht_history, ibuf_ibufBTBResp_bht_history) @[IBuf.scala 63:37 64:21 38:24]
    skip
    node ibuf__GEN_6 = mux(io_imem_resp_bits_btb_valid, io_imem_resp_bits_btb_bits_bht_value, ibuf_ibufBTBResp_bht_value) @[IBuf.scala 63:37 64:21 38:24]
    node ibuf__GEN_7 = mux(ibuf__T_411, ibuf__T_392, ibuf__T_401) @[IBuf.scala 49:15 56:90 58:17]
    skip
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    node ibuf__GEN_24 = mux(ibuf__T_411, ibuf__GEN_2, pad(ibuf_ibufBTBResp_bridx, 2)) @[IBuf.scala 38:24 56:90]
    skip
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    reg wb_reg_replay : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), wb_reg_replay) @[Rocket.scala 152:35]
    node replay_wb_common = or(io_dmem_s2_nack, wb_reg_replay) @[Rocket.scala 416:42]
    skip
    skip
    skip
    skip
    reg wb_reg_xcpt : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), wb_reg_xcpt) @[Rocket.scala 151:35]
    node _T_4174 = or(replay_wb_common, wb_reg_xcpt) @[Rocket.scala 420:27]
    reg wb_ctrl_csr : UInt<3>, const_clock with :
      reset => (UInt<1>("h0"), wb_ctrl_csr) @[Rocket.scala 117:20]
    node csr_io_rw_cmd = mux(wb_reg_valid, wb_ctrl_csr, UInt<3>("h0")) @[Rocket.scala 476:23]
    skip
    node csr_system_insn = eq(csr_io_rw_cmd, UInt<3>("h4")) @[CSR.scala 409:31]
    node csr_io_rw_addr = bits(wb_reg_inst, 31, 20) @[Rocket.scala 475:32]
    skip
    node csr_insn_rs2 = bits(csr_io_rw_addr, 5, 5) @[CSR.scala 411:28]
    node csr__T_1735 = not(csr_insn_rs2) @[CSR.scala 412:34]
    node csr__T_1736 = and(csr_system_insn, csr__T_1735) @[CSR.scala 412:31]
    node csr__T_1733 = bits(csr_io_rw_addr, 2, 0) @[CSR.scala 410:37]
    node csr_opcode = dshl(UInt<1>("h1"), csr__T_1733) @[CSR.scala 410:24]
    node csr__T_1737 = bits(csr_opcode, 0, 0) @[CSR.scala 412:53]
    node csr_insn_call = and(csr__T_1736, csr__T_1737) @[CSR.scala 412:44]
    node csr__T_1738 = bits(csr_opcode, 1, 1) @[CSR.scala 413:41]
    node csr_insn_break = and(csr_system_insn, csr__T_1738) @[CSR.scala 413:32]
    node csr__T_2330 = or(csr_insn_call, csr_insn_break) @[CSR.scala 450:24]
    node csr__T_1739 = bits(csr_opcode, 2, 2) @[CSR.scala 414:39]
    node csr_insn_ret = and(csr_system_insn, csr__T_1739) @[CSR.scala 414:30]
    node csr__T_2331 = or(csr__T_2330, csr_insn_ret) @[CSR.scala 450:38]
    skip
    node take_pc_wb = or(_T_4174, csr__T_2331) @[Rocket.scala 420:38]
    skip
    reg ex_reg_replay : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_replay) @[Rocket.scala 128:26]
    node _T_3781 = or(ex_reg_valid, ex_reg_replay) @[Rocket.scala 323:34]
    reg ex_reg_xcpt_interrupt : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_xcpt_interrupt) @[Rocket.scala 119:35]
    node ex_pc_valid = or(_T_3781, ex_reg_xcpt_interrupt) @[Rocket.scala 323:51]
    reg mem_ctrl_jalr : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_ctrl_jalr) @[Rocket.scala 116:21]
    reg mem_reg_wdata : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_wdata) @[Rocket.scala 146:26]
    node _T_4001 = shr(mem_reg_wdata, 38) @[Rocket.scala 653:16]
    node _T_4005 = eq(_T_4001, UInt<26>("h0")) @[Rocket.scala 656:13]
    node _T_4007 = eq(_T_4001, UInt<26>("h1")) @[Rocket.scala 656:30]
    node _T_4008 = or(_T_4005, _T_4007) @[Rocket.scala 656:25]
    node _T_4002 = bits(mem_reg_wdata, 39, 38) @[Rocket.scala 654:15]
    node _T_4003 = asSInt(_T_4002) @[Rocket.scala 654:39]
    node _T_4010 = neq(_T_4003, SInt<2>("h0")) @[Rocket.scala 656:45]
    node _T_4011 = asSInt(_T_4001) @[Rocket.scala 657:13]
    node _T_4013 = eq(_T_4011, SInt<26>("h-1")) @[Rocket.scala 657:20]
    skip
    node _T_4016 = eq(_T_4011, SInt<26>("h-2")) @[Rocket.scala 657:45]
    node _T_4017 = or(_T_4013, _T_4016) @[Rocket.scala 657:33]
    node _T_4019 = eq(_T_4003, SInt<2>("h-1")) @[Rocket.scala 657:61]
    node _T_4020 = bits(_T_4003, 0, 0) @[Rocket.scala 657:76]
    node _T_4021 = mux(_T_4017, _T_4019, _T_4020) @[Rocket.scala 657:10]
    node _T_4022 = mux(_T_4008, _T_4010, _T_4021) @[Rocket.scala 656:10]
    node _T_4023 = bits(mem_reg_wdata, 38, 0) @[Rocket.scala 658:16]
    node _T_4024 = cat(_T_4022, _T_4023) @[Cat.scala 30:58]
    node _T_4025 = asSInt(_T_4024) @[Rocket.scala 343:88]
    reg mem_reg_pc : UInt<40>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_pc) @[Rocket.scala 144:23]
    node _T_3820 = asSInt(mem_reg_pc) @[Rocket.scala 339:34]
    reg mem_ctrl_branch : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_ctrl_branch) @[Rocket.scala 116:21]
    node mem_br_taken = bits(mem_reg_wdata, 0, 0) @[Rocket.scala 338:35]
    node _T_3821 = and(mem_ctrl_branch, mem_br_taken) @[Rocket.scala 340:25]
    skip
    node _T_3826 = bits(mem_reg_inst, 31, 31) @[Rocket.scala 704:48]
    node _T_3827 = asSInt(_T_3826) @[Rocket.scala 704:53]
    skip
    node _T_3902 = asUInt(_T_3827) @[Cat.scala 30:58]
    skip
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    node _T_3833 = pad(_T_3827, 11) @[Rocket.scala 705:21]
    node _T_3901 = asUInt(_T_3833) @[Cat.scala 30:58]
    node _T_3903 = cat(_T_3902, _T_3901) @[Cat.scala 30:58]
    skip
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    node _T_3839 = bits(mem_reg_inst, 19, 12) @[Rocket.scala 706:65]
    node _T_3840 = asSInt(_T_3839) @[Rocket.scala 706:73]
    node _T_3841 = pad(_T_3827, 8) @[Rocket.scala 706:21]
    node _T_3899 = asUInt(_T_3841) @[Cat.scala 30:58]
    skip
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    node _T_3850 = bits(mem_reg_inst, 20, 20) @[Rocket.scala 708:39]
    node _T_3851 = asSInt(_T_3850) @[Rocket.scala 708:44]
    skip
    node _T_3854 = bits(mem_reg_inst, 7, 7) @[Rocket.scala 709:39]
    node _T_3855 = asSInt(_T_3854) @[Rocket.scala 709:43]
    skip
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    node _T_3898 = asUInt(_T_3855) @[Cat.scala 30:58]
    node _T_3900 = cat(_T_3899, _T_3898) @[Cat.scala 30:58]
    node _T_3904 = cat(_T_3903, _T_3900) @[Cat.scala 30:58]
    skip
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    node _T_3865 = bits(mem_reg_inst, 30, 25) @[Rocket.scala 710:66]
    skip
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    node _T_3875 = bits(mem_reg_inst, 11, 8) @[Rocket.scala 712:57]
    skip
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    node _T_3879 = bits(mem_reg_inst, 24, 21) @[Rocket.scala 713:52]
    skip
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    node _T_3896 = cat(_T_3865, _T_3875) @[Cat.scala 30:58]
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    node _T_3897 = cat(_T_3896, UInt<1>("h0")) @[Cat.scala 30:58]
    node _T_3905 = cat(_T_3904, _T_3897) @[Cat.scala 30:58]
    node _T_3906 = asSInt(_T_3905) @[Rocket.scala 718:53]
    reg mem_ctrl_jal : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_ctrl_jal) @[Rocket.scala 116:21]
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    node _T_3986 = asUInt(_T_3840) @[Cat.scala 30:58]
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    node _T_3985 = asUInt(_T_3851) @[Cat.scala 30:58]
    node _T_3987 = cat(_T_3986, _T_3985) @[Cat.scala 30:58]
    node _T_3991 = cat(_T_3903, _T_3987) @[Cat.scala 30:58]
    skip
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    node _T_3983 = cat(_T_3865, _T_3879) @[Cat.scala 30:58]
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    node _T_3984 = cat(_T_3983, UInt<1>("h0")) @[Cat.scala 30:58]
    node _T_3992 = cat(_T_3991, _T_3984) @[Cat.scala 30:58]
    node _T_3993 = asSInt(_T_3992) @[Rocket.scala 718:53]
    reg mem_reg_rvc : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_rvc) @[Rocket.scala 134:36]
    node _T_3996 = mux(mem_reg_rvc, SInt<4>("h2"), SInt<4>("h4")) @[Rocket.scala 342:8]
    node _T_3997 = mux(mem_ctrl_jal, _T_3993, pad(_T_3996, 32)) @[Rocket.scala 341:8]
    node _T_3998 = mux(_T_3821, _T_3906, _T_3997) @[Rocket.scala 340:8]
    node _GEN_198 = pad(_T_3998, 40) @[Rocket.scala 339:41]
    node _T_3999 = add(_T_3820, _GEN_198) @[Rocket.scala 339:41]
    node _T_4000 = tail(_T_3999, 1) @[Rocket.scala 339:41]
    node mem_br_target = asSInt(_T_4000) @[Rocket.scala 339:41]
    node _T_4026 = mux(mem_ctrl_jalr, _T_4025, mem_br_target) @[Rocket.scala 343:21]
    node _T_4028 = and(_T_4026, SInt<40>("h-2")) @[Rocket.scala 343:111]
    node _T_4029 = asSInt(_T_4028) @[Rocket.scala 343:111]
    node mem_npc = asUInt(_T_4029) @[Rocket.scala 343:123]
    reg ex_reg_pc : UInt<40>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_pc) @[Rocket.scala 129:22]
    node _T_4030 = neq(mem_npc, ex_reg_pc) @[Rocket.scala 344:48]
    node ibuf__T_511 = gt(ibuf_nBufValid, UInt<1>("h0")) @[IBuf.scala 89:26]
    node ibuf__T_512 = mux(ibuf__T_511, ibuf_buf_pc, io_imem_resp_bits_pc) @[IBuf.scala 89:15]
    skip
    node _T_4031 = neq(mem_npc, ibuf__T_512) @[Rocket.scala 344:98]
    node _T_4033 = mux(ibuf__T_543, _T_4031, UInt<1>("h1")) @[Rocket.scala 344:66]
    node mem_misprediction = mux(ex_pc_valid, _T_4030, _T_4033) @[Rocket.scala 344:26]
    reg mem_reg_flush_pipe : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_flush_pipe) @[Rocket.scala 139:36]
    node _T_4051 = or(mem_misprediction, mem_reg_flush_pipe) @[Rocket.scala 351:54]
    node take_pc_mem = and(mem_reg_valid, _T_4051) @[Rocket.scala 351:32]
    skip
    node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) @[Rocket.scala 161:35]
    node _T_4425 = not(ibuf__T_543) @[Rocket.scala 535:17]
    skip
    node _T_4426 = or(_T_4425, ibuf__T_527) @[Rocket.scala 535:40]
    node _T_4427 = or(_T_4426, take_pc_mem_wb) @[Rocket.scala 535:71]
    node _T_4428 = or(_T_4427, ctrl_stalld) @[Rocket.scala 535:89]
    node ctrl_killd = or(_T_4428, csr__GEN_2) @[Rocket.scala 535:104]
    skip
    node _T_3444 = not(ctrl_killd) @[Rocket.scala 185:34]
    skip
    node _T_2823 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h68")) @[Decode.scala 13:65]
    node id_ctrl_jal = eq(_T_2823, UInt<32>("h68")) @[Decode.scala 13:121]
    skip
    skip
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    node ibuf__GEN_29 = mux(take_pc_mem_wb, UInt<2>("h0"), ibuf__GEN_7) @[IBuf.scala 68:20 69:17]
    node ibuf__T_482 = not(io_imem_resp_bits_btb_valid) @[IBuf.scala 84:10]
    node ibuf__T_483 = geq(io_imem_resp_bits_btb_bits_bridx, ibuf_pcWordBits) @[IBuf.scala 84:65]
    node ibuf__T_484 = or(ibuf__T_482, ibuf__T_483) @[IBuf.scala 84:34]
    skip
    node ibuf__T_485 = or(ibuf__T_484, reset) @[IBuf.scala 84:9]
    node ibuf__T_487 = not(ibuf__T_485) @[IBuf.scala 84:9]
    skip
    node ibuf__T_500 = neq(ibuf__T_495, UInt<2>("h0")) @[IBuf.scala 88:49]
    node ibuf__T_501_taken = mux(ibuf__T_500, ibuf_ibufBTBResp_taken, io_imem_resp_bits_btb_bits_taken) @[IBuf.scala 88:21]
    node ibuf__T_501_mask = mux(ibuf__T_500, ibuf_ibufBTBResp_mask, io_imem_resp_bits_btb_bits_mask) @[IBuf.scala 88:21]
    node ibuf__T_501_bridx = mux(ibuf__T_500, ibuf_ibufBTBResp_bridx, io_imem_resp_bits_btb_bits_bridx) @[IBuf.scala 88:21]
    node ibuf__T_501_target = mux(ibuf__T_500, ibuf_ibufBTBResp_target, io_imem_resp_bits_btb_bits_target) @[IBuf.scala 88:21]
    node ibuf__T_501_entry = mux(ibuf__T_500, ibuf_ibufBTBResp_entry, io_imem_resp_bits_btb_bits_entry) @[IBuf.scala 88:21]
    node ibuf__T_501_bht_history = mux(ibuf__T_500, ibuf_ibufBTBResp_bht_history, io_imem_resp_bits_btb_bits_bht_history) @[IBuf.scala 88:21]
    node ibuf__T_501_bht_value = mux(ibuf__T_500, ibuf_ibufBTBResp_bht_value, io_imem_resp_bits_btb_bits_bht_value) @[IBuf.scala 88:21]
    skip
    node ibuf__T_545 = bits(ibuf_xcpt_if, 0, 0) @[IBuf.scala 101:37]
    skip
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    skip
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    node ibuf__T_553 = and(ibuf__T_517, ibuf__T_540) @[IBuf.scala 102:42]
    skip
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    node _GEN_200 = shr(ibuf_btbHitMask, 1) @[IBuf.scala 104:77]
    node ibuf__T_561 = pad(_GEN_200, 4) @[IBuf.scala 104:77]
    node ibuf__T_562 = bits(ibuf__T_561, 0, 0) @[IBuf.scala 104:77]
    node ibuf__T_563 = and(ibuf__T_517, ibuf__T_562) @[IBuf.scala 104:64]
    node ibuf__T_564 = or(ibuf__T_519, ibuf__T_563) @[IBuf.scala 104:48]
    skip
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    reg csr_reg_mstatus_tsr : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_tsr) @[CSR.scala 197:24]
    reg csr_reg_mstatus_tw : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_tw) @[CSR.scala 197:24]
    reg csr_reg_mstatus_tvm : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_tvm) @[CSR.scala 197:24]
    reg csr_reg_mstatus_mxr : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_mxr) @[CSR.scala 197:24]
    reg csr_reg_mstatus_pum : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_pum) @[CSR.scala 197:24]
    reg csr_reg_mstatus_mprv : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_mprv) @[CSR.scala 197:24]
    skip
    reg csr_reg_mstatus_fs : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_fs) @[CSR.scala 197:24]
    reg csr_reg_mstatus_mpp : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_mpp) @[CSR.scala 197:24]
    skip
    reg csr_reg_mstatus_spp : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_spp) @[CSR.scala 197:24]
    reg csr_reg_mstatus_mpie : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_mpie) @[CSR.scala 197:24]
    skip
    reg csr_reg_mstatus_spie : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mstatus_spie) @[CSR.scala 197:24]
    skip
    skip
    skip
    node csr__T_2450 = bits(csr_io_rw_addr, 9, 9) @[CSR.scala 506:39]
    node csr__T_2452 = not(csr__T_2450) @[CSR.scala 506:28]
    skip
    node csr__T_2465 = not(csr__T_2452) @[CSR.scala 506:44]
    node csr__T_2458 = bits(csr_io_rw_addr, 10, 10) @[CSR.scala 512:47]
    skip
    node csr__T_2467 = not(csr__T_2458) @[CSR.scala 512:53]
    node csr__T_2468 = and(csr__T_2465, csr__T_2467) @[CSR.scala 512:53]
    skip
    node csr__T_2462 = and(csr__T_2465, csr__T_2458) @[CSR.scala 512:53]
    reg csr_reg_dcsr_prv : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_dcsr_prv) @[CSR.scala 205:21]
    skip
    skip
    node csr_exception = or(csr__T_2330, wb_reg_xcpt) @[CSR.scala 461:43]
    node _GEN_201 = pad(csr_reg_mstatus_prv, 4) @[CSR.scala 437:36]
    node csr__T_2247 = add(_GEN_201, UInt<4>("h8")) @[CSR.scala 437:36]
    node csr__T_2248 = tail(csr__T_2247, 1) @[CSR.scala 437:36]
    reg wb_reg_cause : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), wb_reg_cause) @[Rocket.scala 153:35]
    skip
    node csr__T_2250 = mux(csr_insn_break, UInt<64>("h3"), wb_reg_cause) @[CSR.scala 438:14]
    node csr_cause = mux(csr_insn_call, pad(csr__T_2248, 64), csr__T_2250) @[CSR.scala 437:8]
    node csr__T_2251 = bits(csr_cause, 63, 63) @[CSR.scala 440:30]
    node csr_cause_lsbs = bits(csr_cause, 5, 0) @[CSR.scala 439:25]
    node csr__T_2267 = eq(csr_cause_lsbs, UInt<6>("hd")) @[CSR.scala 440:53]
    node csr_causeIsDebugInt = and(csr__T_2251, csr__T_2267) @[CSR.scala 440:39]
    node csr__T_2311 = or(csr_reg_singleStepped, csr_causeIsDebugInt) @[CSR.scala 443:60]
    skip
    node csr__T_2270 = not(csr__T_2251) @[CSR.scala 441:29]
    skip
    node csr_causeIsDebugTrigger = and(csr__T_2270, csr__T_2267) @[CSR.scala 441:44]
    node csr__T_2312 = or(csr__T_2311, csr_causeIsDebugTrigger) @[CSR.scala 443:79]
    skip
    skip
    node csr__T_2304 = and(csr__T_2270, csr_insn_break) @[CSR.scala 442:42]
    reg csr_reg_dcsr_ebreakm : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_dcsr_ebreakm) @[CSR.scala 205:21]
    skip
    node csr__T_2306 = cat(csr_reg_dcsr_ebreakm, UInt<1>("h0")) @[Cat.scala 30:58]
    reg csr_reg_dcsr_ebreaks : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_dcsr_ebreaks) @[CSR.scala 205:21]
    reg csr_reg_dcsr_ebreaku : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_dcsr_ebreaku) @[CSR.scala 205:21]
    node csr__T_2305 = cat(csr_reg_dcsr_ebreaks, csr_reg_dcsr_ebreaku) @[Cat.scala 30:58]
    node csr__T_2307 = cat(csr__T_2306, csr__T_2305) @[Cat.scala 30:58]
    node csr__T_2308 = dshr(csr__T_2307, csr_reg_mstatus_prv) @[CSR.scala 442:134]
    node csr__T_2309 = bits(csr__T_2308, 0, 0) @[CSR.scala 442:134]
    node csr_causeIsDebugBreak = and(csr__T_2304, csr__T_2309) @[CSR.scala 442:56]
    node csr__T_2313 = or(csr__T_2312, csr_causeIsDebugBreak) @[CSR.scala 443:102]
    node csr__T_2314 = or(csr__T_2313, csr_reg_debug) @[CSR.scala 443:123]
    skip
    node csr__T_2435 = not(csr__T_2314) @[CSR.scala 481:24]
    skip
    skip
    skip
    node csr__T_2320 = dshr(csr_reg_mideleg, csr_cause_lsbs) @[CSR.scala 444:93]
    node csr__T_2321 = bits(csr__T_2320, 0, 0) @[CSR.scala 444:93]
    reg csr_reg_medeleg : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_medeleg) @[CSR.scala 243:24]
    node csr__T_2322 = dshr(csr_reg_medeleg, csr_cause_lsbs) @[CSR.scala 444:118]
    node csr__T_2323 = bits(csr__T_2322, 0, 0) @[CSR.scala 444:118]
    node csr__T_2324 = mux(csr__T_2251, csr__T_2321, csr__T_2323) @[CSR.scala 444:66]
    node csr_delegate = and(csr__T_983, csr__T_2324) @[CSR.scala 444:60]
    node csr__T_2437 = not(csr_delegate) @[CSR.scala 486:27]
    node csr__T_2438 = and(csr__T_2435, csr__T_2437) @[CSR.scala 486:27]
    skip
    node csr__T_2423 = and(csr__T_2435, csr_delegate) @[CSR.scala 486:27]
    node csr__GEN_51 = mux(csr__T_2423, UInt<2>("h1"), csr_reg_mstatus_prv) @[CSR.scala 486:27 493:15]
    node csr__GEN_59 = mux(csr__T_2438, UInt<2>("h3"), csr__GEN_51) @[CSR.scala 494:17 501:15]
    node csr__GEN_70 = mux(csr_exception, csr__GEN_59, csr_reg_mstatus_prv) @[CSR.scala 473:20]
    node csr__GEN_81 = mux(csr__T_2452, pad(csr_reg_mstatus_spp, 2), csr__GEN_70) @[CSR.scala 506:44 510:15]
    node csr__GEN_83 = mux(csr__T_2462, csr_reg_dcsr_prv, csr__GEN_81) @[CSR.scala 512:53 513:15]
    node csr__GEN_92 = mux(csr__T_2468, csr_reg_mstatus_mpp, csr__GEN_83) @[CSR.scala 516:17 521:15]
    node csr__GEN_97 = mux(csr_insn_ret, csr__GEN_92, csr__GEN_70) @[CSR.scala 505:19]
    skip
    node csr__T_465 = eq(csr__GEN_97, UInt<2>("h2")) @[CSR.scala 697:27]
    node csr__T_467 = mux(csr__T_465, UInt<2>("h0"), csr__GEN_97) @[CSR.scala 697:21]
    skip
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    reg csr_reg_dcsr_cause : UInt<3>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_dcsr_cause) @[CSR.scala 205:21]
    skip
    reg csr_reg_dcsr_halt : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_dcsr_halt) @[CSR.scala 205:21]
    skip
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    node csr_effective_prv = cat(csr_reg_debug, csr_reg_mstatus_prv) @[Cat.scala 30:58]
    reg csr_reg_dpc : UInt<40>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_dpc) @[CSR.scala 234:20]
    reg csr_reg_dscratch : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_dscratch) @[CSR.scala 235:25]
    skip
    skip
    reg csr_reg_bp_0_control_dmode : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_bp_0_control_dmode) @[CSR.scala 239:19]
    skip
    skip
    reg csr_reg_bp_0_control_action : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_bp_0_control_action) @[CSR.scala 239:19]
    skip
    skip
    reg csr_reg_bp_0_control_tmatch : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_bp_0_control_tmatch) @[CSR.scala 239:19]
    reg csr_reg_bp_0_control_m : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_bp_0_control_m) @[CSR.scala 239:19]
    skip
    reg csr_reg_bp_0_control_s : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_bp_0_control_s) @[CSR.scala 239:19]
    reg csr_reg_bp_0_control_u : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_bp_0_control_u) @[CSR.scala 239:19]
    reg csr_reg_bp_0_control_x : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_bp_0_control_x) @[CSR.scala 239:19]
    reg csr_reg_bp_0_control_w : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_bp_0_control_w) @[CSR.scala 239:19]
    reg csr_reg_bp_0_control_r : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_bp_0_control_r) @[CSR.scala 239:19]
    reg csr_reg_bp_0_address : UInt<39>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_bp_0_address) @[CSR.scala 239:19]
    skip
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    reg csr_reg_mepc : UInt<40>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mepc) @[CSR.scala 245:21]
    reg csr_reg_mcause : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mcause) @[CSR.scala 246:23]
    reg csr_reg_mbadaddr : UInt<40>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mbadaddr) @[CSR.scala 247:25]
    reg csr_reg_mscratch : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mscratch) @[CSR.scala 248:25]
    reg csr_reg_mtvec : UInt<32>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mtvec) @[CSR.scala 251:27]
    reg csr_reg_mcounteren : UInt<32>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_mcounteren) @[CSR.scala 254:27]
    reg csr_reg_scounteren : UInt<32>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_scounteren) @[CSR.scala 255:27]
    reg csr_reg_sepc : UInt<40>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_sepc) @[CSR.scala 258:21]
    reg csr_reg_scause : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_scause) @[CSR.scala 259:23]
    reg csr_reg_sbadaddr : UInt<40>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_sbadaddr) @[CSR.scala 260:25]
    reg csr_reg_sscratch : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_sscratch) @[CSR.scala 261:25]
    reg csr_reg_stvec : UInt<39>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_stvec) @[CSR.scala 262:22]
    reg csr_reg_sptbr_mode : UInt<4>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_sptbr_mode) @[CSR.scala 263:22]
    skip
    reg csr_reg_sptbr_ppn : UInt<44>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_sptbr_ppn) @[CSR.scala 263:22]
    reg csr_reg_fflags : UInt<5>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_fflags) @[CSR.scala 266:23]
    reg csr_reg_frm : UInt<3>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_frm) @[CSR.scala 267:20]
    reg csr__T_931 : UInt<6>, const_clock with :
      reset => (UInt<1>("h0"), csr__T_931) @[Counters.scala 47:37]
    node _T_4187 = not(replay_wb_common) @[Rocket.scala 450:34]
    node _T_4188 = and(wb_reg_valid, _T_4187) @[Rocket.scala 450:31]
    node _T_4190 = not(wb_reg_xcpt) @[Rocket.scala 450:48]
    node wb_valid = and(_T_4188, _T_4190) @[Rocket.scala 450:45]
    skip
    node _GEN_202 = pad(wb_valid, 6) @[Counters.scala 48:33]
    node csr__T_932 = add(csr__T_931, _GEN_202) @[Counters.scala 48:33]
    reg csr__T_934 : UInt<58>, const_clock with :
      reset => (UInt<1>("h0"), csr__T_934) @[Counters.scala 52:27]
    node csr__T_935 = bits(csr__T_932, 6, 6) @[Counters.scala 53:20]
    node csr__T_937 = add(csr__T_934, UInt<58>("h1")) @[Counters.scala 53:43]
    node csr__T_938 = tail(csr__T_937, 1) @[Counters.scala 53:43]
    node csr__GEN_0 = mux(csr__T_935, csr__T_938, csr__T_934) @[Counters.scala 52:27 53:{34,38}]
    node csr__T_939 = cat(csr__T_934, csr__T_931) @[Cat.scala 30:58]
    reg csr__T_942 : UInt<6>, const_clock with :
      reset => (UInt<1>("h0"), csr__T_942) @[Counters.scala 47:37]
    node csr__T_943 = add(csr__T_942, UInt<6>("h1")) @[Counters.scala 48:33]
    reg csr__T_945 : UInt<58>, const_clock with :
      reset => (UInt<1>("h0"), csr__T_945) @[Counters.scala 52:27]
    node csr__T_946 = bits(csr__T_943, 6, 6) @[Counters.scala 53:20]
    node csr__T_948 = add(csr__T_945, UInt<58>("h1")) @[Counters.scala 53:43]
    node csr__T_949 = tail(csr__T_948, 1) @[Counters.scala 53:43]
    node csr__GEN_1 = mux(csr__T_946, csr__T_949, csr__T_945) @[Counters.scala 52:27 53:{34,38}]
    node csr__T_950 = cat(csr__T_945, csr__T_942) @[Cat.scala 30:58]
    skip
    skip
    node csr__T_956 = mux(csr__T_996, UInt<32>("h7"), csr_reg_scounteren) @[CSR.scala 274:38]
    node csr_hpm_mask = and(csr_reg_mcounteren, csr__T_956) @[CSR.scala 274:33]
    node csr__T_1003 = bits(csr_all_interrupts, 0, 0) @[OneHot.scala 39:40]
    node csr__T_1004 = bits(csr_all_interrupts, 1, 1) @[OneHot.scala 39:40]
    node csr__T_1005 = bits(csr_all_interrupts, 2, 2) @[OneHot.scala 39:40]
    node csr__T_1006 = bits(csr_all_interrupts, 3, 3) @[OneHot.scala 39:40]
    node csr__T_1007 = bits(csr_all_interrupts, 4, 4) @[OneHot.scala 39:40]
    node csr__T_1008 = bits(csr_all_interrupts, 5, 5) @[OneHot.scala 39:40]
    node csr__T_1009 = bits(csr_all_interrupts, 6, 6) @[OneHot.scala 39:40]
    node csr__T_1010 = bits(csr_all_interrupts, 7, 7) @[OneHot.scala 39:40]
    node csr__T_1011 = bits(csr_all_interrupts, 8, 8) @[OneHot.scala 39:40]
    node csr__T_1012 = bits(csr_all_interrupts, 9, 9) @[OneHot.scala 39:40]
    node csr__T_1013 = bits(csr_all_interrupts, 10, 10) @[OneHot.scala 39:40]
    node csr__T_1014 = bits(csr_all_interrupts, 11, 11) @[OneHot.scala 39:40]
    node csr__T_1015 = bits(csr_all_interrupts, 12, 12) @[OneHot.scala 39:40]
    node csr__T_1016 = bits(csr_all_interrupts, 13, 13) @[OneHot.scala 39:40]
    node csr__T_1017 = bits(csr_all_interrupts, 14, 14) @[OneHot.scala 39:40]
    node csr__T_1018 = bits(csr_all_interrupts, 15, 15) @[OneHot.scala 39:40]
    node csr__T_1019 = bits(csr_all_interrupts, 16, 16) @[OneHot.scala 39:40]
    node csr__T_1020 = bits(csr_all_interrupts, 17, 17) @[OneHot.scala 39:40]
    node csr__T_1021 = bits(csr_all_interrupts, 18, 18) @[OneHot.scala 39:40]
    node csr__T_1022 = bits(csr_all_interrupts, 19, 19) @[OneHot.scala 39:40]
    node csr__T_1023 = bits(csr_all_interrupts, 20, 20) @[OneHot.scala 39:40]
    node csr__T_1024 = bits(csr_all_interrupts, 21, 21) @[OneHot.scala 39:40]
    node csr__T_1025 = bits(csr_all_interrupts, 22, 22) @[OneHot.scala 39:40]
    node csr__T_1026 = bits(csr_all_interrupts, 23, 23) @[OneHot.scala 39:40]
    node csr__T_1027 = bits(csr_all_interrupts, 24, 24) @[OneHot.scala 39:40]
    node csr__T_1028 = bits(csr_all_interrupts, 25, 25) @[OneHot.scala 39:40]
    node csr__T_1029 = bits(csr_all_interrupts, 26, 26) @[OneHot.scala 39:40]
    node csr__T_1030 = bits(csr_all_interrupts, 27, 27) @[OneHot.scala 39:40]
    node csr__T_1031 = bits(csr_all_interrupts, 28, 28) @[OneHot.scala 39:40]
    node csr__T_1032 = bits(csr_all_interrupts, 29, 29) @[OneHot.scala 39:40]
    node csr__T_1033 = bits(csr_all_interrupts, 30, 30) @[OneHot.scala 39:40]
    node csr__T_1034 = bits(csr_all_interrupts, 31, 31) @[OneHot.scala 39:40]
    node csr__T_1035 = bits(csr_all_interrupts, 32, 32) @[OneHot.scala 39:40]
    node csr__T_1036 = bits(csr_all_interrupts, 33, 33) @[OneHot.scala 39:40]
    node csr__T_1037 = bits(csr_all_interrupts, 34, 34) @[OneHot.scala 39:40]
    node csr__T_1038 = bits(csr_all_interrupts, 35, 35) @[OneHot.scala 39:40]
    node csr__T_1039 = bits(csr_all_interrupts, 36, 36) @[OneHot.scala 39:40]
    node csr__T_1040 = bits(csr_all_interrupts, 37, 37) @[OneHot.scala 39:40]
    node csr__T_1041 = bits(csr_all_interrupts, 38, 38) @[OneHot.scala 39:40]
    node csr__T_1042 = bits(csr_all_interrupts, 39, 39) @[OneHot.scala 39:40]
    node csr__T_1043 = bits(csr_all_interrupts, 40, 40) @[OneHot.scala 39:40]
    node csr__T_1044 = bits(csr_all_interrupts, 41, 41) @[OneHot.scala 39:40]
    node csr__T_1045 = bits(csr_all_interrupts, 42, 42) @[OneHot.scala 39:40]
    node csr__T_1046 = bits(csr_all_interrupts, 43, 43) @[OneHot.scala 39:40]
    node csr__T_1047 = bits(csr_all_interrupts, 44, 44) @[OneHot.scala 39:40]
    node csr__T_1048 = bits(csr_all_interrupts, 45, 45) @[OneHot.scala 39:40]
    node csr__T_1049 = bits(csr_all_interrupts, 46, 46) @[OneHot.scala 39:40]
    node csr__T_1050 = bits(csr_all_interrupts, 47, 47) @[OneHot.scala 39:40]
    node csr__T_1051 = bits(csr_all_interrupts, 48, 48) @[OneHot.scala 39:40]
    node csr__T_1052 = bits(csr_all_interrupts, 49, 49) @[OneHot.scala 39:40]
    node csr__T_1053 = bits(csr_all_interrupts, 50, 50) @[OneHot.scala 39:40]
    node csr__T_1054 = bits(csr_all_interrupts, 51, 51) @[OneHot.scala 39:40]
    node csr__T_1055 = bits(csr_all_interrupts, 52, 52) @[OneHot.scala 39:40]
    node csr__T_1056 = bits(csr_all_interrupts, 53, 53) @[OneHot.scala 39:40]
    node csr__T_1057 = bits(csr_all_interrupts, 54, 54) @[OneHot.scala 39:40]
    node csr__T_1058 = bits(csr_all_interrupts, 55, 55) @[OneHot.scala 39:40]
    node csr__T_1059 = bits(csr_all_interrupts, 56, 56) @[OneHot.scala 39:40]
    node csr__T_1060 = bits(csr_all_interrupts, 57, 57) @[OneHot.scala 39:40]
    node csr__T_1061 = bits(csr_all_interrupts, 58, 58) @[OneHot.scala 39:40]
    node csr__T_1062 = bits(csr_all_interrupts, 59, 59) @[OneHot.scala 39:40]
    node csr__T_1063 = bits(csr_all_interrupts, 60, 60) @[OneHot.scala 39:40]
    node csr__T_1064 = bits(csr_all_interrupts, 61, 61) @[OneHot.scala 39:40]
    node csr__T_1065 = bits(csr_all_interrupts, 62, 62) @[OneHot.scala 39:40]
    skip
    node csr__T_1131 = mux(csr__T_1065, UInt<6>("h3e"), UInt<6>("h3f")) @[Mux.scala 31:69]
    node csr__T_1132 = mux(csr__T_1064, UInt<6>("h3d"), csr__T_1131) @[Mux.scala 31:69]
    node csr__T_1133 = mux(csr__T_1063, UInt<6>("h3c"), csr__T_1132) @[Mux.scala 31:69]
    node csr__T_1134 = mux(csr__T_1062, UInt<6>("h3b"), csr__T_1133) @[Mux.scala 31:69]
    node csr__T_1135 = mux(csr__T_1061, UInt<6>("h3a"), csr__T_1134) @[Mux.scala 31:69]
    node csr__T_1136 = mux(csr__T_1060, UInt<6>("h39"), csr__T_1135) @[Mux.scala 31:69]
    node csr__T_1137 = mux(csr__T_1059, UInt<6>("h38"), csr__T_1136) @[Mux.scala 31:69]
    node csr__T_1138 = mux(csr__T_1058, UInt<6>("h37"), csr__T_1137) @[Mux.scala 31:69]
    node csr__T_1139 = mux(csr__T_1057, UInt<6>("h36"), csr__T_1138) @[Mux.scala 31:69]
    node csr__T_1140 = mux(csr__T_1056, UInt<6>("h35"), csr__T_1139) @[Mux.scala 31:69]
    node csr__T_1141 = mux(csr__T_1055, UInt<6>("h34"), csr__T_1140) @[Mux.scala 31:69]
    node csr__T_1142 = mux(csr__T_1054, UInt<6>("h33"), csr__T_1141) @[Mux.scala 31:69]
    node csr__T_1143 = mux(csr__T_1053, UInt<6>("h32"), csr__T_1142) @[Mux.scala 31:69]
    node csr__T_1144 = mux(csr__T_1052, UInt<6>("h31"), csr__T_1143) @[Mux.scala 31:69]
    node csr__T_1145 = mux(csr__T_1051, UInt<6>("h30"), csr__T_1144) @[Mux.scala 31:69]
    node csr__T_1146 = mux(csr__T_1050, UInt<6>("h2f"), csr__T_1145) @[Mux.scala 31:69]
    node csr__T_1147 = mux(csr__T_1049, UInt<6>("h2e"), csr__T_1146) @[Mux.scala 31:69]
    node csr__T_1148 = mux(csr__T_1048, UInt<6>("h2d"), csr__T_1147) @[Mux.scala 31:69]
    node csr__T_1149 = mux(csr__T_1047, UInt<6>("h2c"), csr__T_1148) @[Mux.scala 31:69]
    node csr__T_1150 = mux(csr__T_1046, UInt<6>("h2b"), csr__T_1149) @[Mux.scala 31:69]
    node csr__T_1151 = mux(csr__T_1045, UInt<6>("h2a"), csr__T_1150) @[Mux.scala 31:69]
    node csr__T_1152 = mux(csr__T_1044, UInt<6>("h29"), csr__T_1151) @[Mux.scala 31:69]
    node csr__T_1153 = mux(csr__T_1043, UInt<6>("h28"), csr__T_1152) @[Mux.scala 31:69]
    node csr__T_1154 = mux(csr__T_1042, UInt<6>("h27"), csr__T_1153) @[Mux.scala 31:69]
    node csr__T_1155 = mux(csr__T_1041, UInt<6>("h26"), csr__T_1154) @[Mux.scala 31:69]
    node csr__T_1156 = mux(csr__T_1040, UInt<6>("h25"), csr__T_1155) @[Mux.scala 31:69]
    node csr__T_1157 = mux(csr__T_1039, UInt<6>("h24"), csr__T_1156) @[Mux.scala 31:69]
    node csr__T_1158 = mux(csr__T_1038, UInt<6>("h23"), csr__T_1157) @[Mux.scala 31:69]
    node csr__T_1159 = mux(csr__T_1037, UInt<6>("h22"), csr__T_1158) @[Mux.scala 31:69]
    node csr__T_1160 = mux(csr__T_1036, UInt<6>("h21"), csr__T_1159) @[Mux.scala 31:69]
    node csr__T_1161 = mux(csr__T_1035, UInt<6>("h20"), csr__T_1160) @[Mux.scala 31:69]
    node csr__T_1162 = mux(csr__T_1034, UInt<6>("h1f"), csr__T_1161) @[Mux.scala 31:69]
    node csr__T_1163 = mux(csr__T_1033, UInt<6>("h1e"), csr__T_1162) @[Mux.scala 31:69]
    node csr__T_1164 = mux(csr__T_1032, UInt<6>("h1d"), csr__T_1163) @[Mux.scala 31:69]
    node csr__T_1165 = mux(csr__T_1031, UInt<6>("h1c"), csr__T_1164) @[Mux.scala 31:69]
    node csr__T_1166 = mux(csr__T_1030, UInt<6>("h1b"), csr__T_1165) @[Mux.scala 31:69]
    node csr__T_1167 = mux(csr__T_1029, UInt<6>("h1a"), csr__T_1166) @[Mux.scala 31:69]
    node csr__T_1168 = mux(csr__T_1028, UInt<6>("h19"), csr__T_1167) @[Mux.scala 31:69]
    node csr__T_1169 = mux(csr__T_1027, UInt<6>("h18"), csr__T_1168) @[Mux.scala 31:69]
    node csr__T_1170 = mux(csr__T_1026, UInt<6>("h17"), csr__T_1169) @[Mux.scala 31:69]
    node csr__T_1171 = mux(csr__T_1025, UInt<6>("h16"), csr__T_1170) @[Mux.scala 31:69]
    node csr__T_1172 = mux(csr__T_1024, UInt<6>("h15"), csr__T_1171) @[Mux.scala 31:69]
    node csr__T_1173 = mux(csr__T_1023, UInt<6>("h14"), csr__T_1172) @[Mux.scala 31:69]
    node csr__T_1174 = mux(csr__T_1022, UInt<6>("h13"), csr__T_1173) @[Mux.scala 31:69]
    node csr__T_1175 = mux(csr__T_1021, UInt<6>("h12"), csr__T_1174) @[Mux.scala 31:69]
    node csr__T_1176 = mux(csr__T_1020, UInt<6>("h11"), csr__T_1175) @[Mux.scala 31:69]
    node csr__T_1177 = mux(csr__T_1019, UInt<6>("h10"), csr__T_1176) @[Mux.scala 31:69]
    node csr__T_1178 = mux(csr__T_1018, UInt<6>("hf"), csr__T_1177) @[Mux.scala 31:69]
    node csr__T_1179 = mux(csr__T_1017, UInt<6>("he"), csr__T_1178) @[Mux.scala 31:69]
    node csr__T_1180 = mux(csr__T_1016, UInt<6>("hd"), csr__T_1179) @[Mux.scala 31:69]
    node csr__T_1181 = mux(csr__T_1015, UInt<6>("hc"), csr__T_1180) @[Mux.scala 31:69]
    node csr__T_1182 = mux(csr__T_1014, UInt<6>("hb"), csr__T_1181) @[Mux.scala 31:69]
    node csr__T_1183 = mux(csr__T_1013, UInt<6>("ha"), csr__T_1182) @[Mux.scala 31:69]
    node csr__T_1184 = mux(csr__T_1012, UInt<6>("h9"), csr__T_1183) @[Mux.scala 31:69]
    node csr__T_1185 = mux(csr__T_1011, UInt<6>("h8"), csr__T_1184) @[Mux.scala 31:69]
    node csr__T_1186 = mux(csr__T_1010, UInt<6>("h7"), csr__T_1185) @[Mux.scala 31:69]
    node csr__T_1187 = mux(csr__T_1009, UInt<6>("h6"), csr__T_1186) @[Mux.scala 31:69]
    node csr__T_1188 = mux(csr__T_1008, UInt<6>("h5"), csr__T_1187) @[Mux.scala 31:69]
    node csr__T_1189 = mux(csr__T_1007, UInt<6>("h4"), csr__T_1188) @[Mux.scala 31:69]
    node csr__T_1190 = mux(csr__T_1006, UInt<6>("h3"), csr__T_1189) @[Mux.scala 31:69]
    node csr__T_1191 = mux(csr__T_1005, UInt<6>("h2"), csr__T_1190) @[Mux.scala 31:69]
    node csr__T_1192 = mux(csr__T_1004, UInt<6>("h1"), csr__T_1191) @[Mux.scala 31:69]
    node csr__T_1193 = mux(csr__T_1003, UInt<6>("h0"), csr__T_1192) @[Mux.scala 31:69]
    node _GEN_203 = pad(csr__T_1193, 64) @[CSR.scala 285:43]
    node csr__T_1194 = add(UInt<64>("h8000000000000000"), _GEN_203) @[CSR.scala 285:43]
    node csr_interruptCause = tail(csr__T_1194, 1) @[CSR.scala 285:43]
    skip
    skip
    node csr__GEN_3 = mux(csr__T_1208, UInt<64>("h800000000000000d"), csr_interruptCause) @[CSR.scala 287:22 291:62 293:24]
    reg csr_reg_misa : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), csr_reg_misa) @[CSR.scala 307:21]
    skip
    skip
    node csr__T_1229 = cat(UInt<1>("h0"), csr_reg_mstatus_sie) @[CSR.scala 308:38]
    skip
    node csr__T_1230 = cat(csr__T_1229, UInt<1>("h0")) @[CSR.scala 308:38]
    skip
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    node csr__T_1231 = cat(UInt<1>("h0"), csr_reg_mstatus_mie) @[CSR.scala 308:38]
    skip
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    node csr__T_1232 = cat(UInt<1>("h0"), csr_reg_mstatus_spie) @[CSR.scala 308:38]
    node csr__T_1233 = cat(csr__T_1232, csr__T_1231) @[CSR.scala 308:38]
    node csr__T_1234 = cat(csr__T_1233, csr__T_1230) @[CSR.scala 308:38]
    skip
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    node csr__T_1235 = cat(UInt<2>("h0"), csr_reg_mstatus_spp) @[CSR.scala 308:38]
    skip
    node csr__T_1236 = cat(csr__T_1235, csr_reg_mstatus_mpie) @[CSR.scala 308:38]
    skip
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    node csr__T_1237 = cat(csr_reg_mstatus_fs, csr_reg_mstatus_mpp) @[CSR.scala 308:38]
    skip
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    node csr__T_1238 = cat(csr_reg_mstatus_mprv, UInt<2>("h0")) @[CSR.scala 308:38]
    node csr__T_1239 = cat(csr__T_1238, csr__T_1237) @[CSR.scala 308:38]
    node csr__T_1240 = cat(csr__T_1239, csr__T_1236) @[CSR.scala 308:38]
    node csr__T_1241 = cat(csr__T_1240, csr__T_1234) @[CSR.scala 308:38]
    skip
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    node csr__T_1242 = cat(csr_reg_mstatus_tvm, csr_reg_mstatus_mxr) @[CSR.scala 308:38]
    skip
    node csr__T_1243 = cat(csr__T_1242, csr_reg_mstatus_pum) @[CSR.scala 308:38]
    skip
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    node csr__T_1244 = cat(csr_reg_mstatus_tsr, csr_reg_mstatus_tw) @[CSR.scala 308:38]
    skip
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    node csr__T_1246 = cat(UInt<9>("h0"), csr__T_1244) @[CSR.scala 308:38]
    node csr__T_1247 = cat(csr__T_1246, csr__T_1243) @[CSR.scala 308:38]
    skip
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    node csr__T_2335 = not(csr_reg_mstatus_fs) @[CSR.scala 453:32]
    node csr__T_2337 = eq(csr__T_2335, UInt<2>("h0")) @[CSR.scala 453:32]
    skip
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    node csr__T_1250 = cat(csr_reg_mstatus_prv, csr__T_2337) @[CSR.scala 308:38]
    skip
    node csr_io_status_isa = bits(csr_reg_misa, 31, 0)
    node csr__T_1251 = cat(csr_reg_debug, csr_io_status_isa) @[CSR.scala 308:38]
    node csr__T_1252 = cat(csr__T_1251, csr__T_1250) @[CSR.scala 308:38]
    node csr__T_1253 = cat(csr__T_1252, UInt<31>("ha")) @[CSR.scala 308:38]
    node csr__T_1254 = cat(csr__T_1253, csr__T_1247) @[CSR.scala 308:38]
    node csr__T_1255 = cat(csr__T_1254, csr__T_1241) @[CSR.scala 308:38]
    node csr_read_mstatus = bits(csr__T_1255, 63, 0) @[CSR.scala 308:40]
    skip
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    node csr__T_1291 = cat(csr_reg_bp_0_control_x, csr_reg_bp_0_control_w) @[CSR.scala 312:48]
    skip
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    node csr__T_1292 = cat(csr__T_1291, csr_reg_bp_0_control_r) @[CSR.scala 312:48]
    skip
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    node csr__T_1293 = cat(csr_reg_bp_0_control_s, csr_reg_bp_0_control_u) @[CSR.scala 312:48]
    skip
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    node csr__T_1294 = cat(csr_reg_bp_0_control_m, UInt<1>("h0")) @[CSR.scala 312:48]
    node csr__T_1295 = cat(csr__T_1294, csr__T_1293) @[CSR.scala 312:48]
    node csr__T_1296 = cat(csr__T_1295, csr__T_1292) @[CSR.scala 312:48]
    skip
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    node csr__T_1297 = cat(UInt<2>("h0"), csr_reg_bp_0_control_tmatch) @[CSR.scala 312:48]
    skip
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    node csr__T_1298 = cat(csr_reg_bp_0_control_action, UInt<1>("h0")) @[CSR.scala 312:48]
    node csr__T_1299 = cat(csr__T_1298, csr__T_1297) @[CSR.scala 312:48]
    skip
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    node csr__T_1301 = cat(UInt<4>("h2"), csr_reg_bp_0_control_dmode) @[CSR.scala 312:48]
    node csr__T_1302 = cat(csr__T_1301, UInt<46>("h40000000000")) @[CSR.scala 312:48]
    node csr__T_1303 = cat(csr__T_1302, csr__T_1299) @[CSR.scala 312:48]
    node csr__T_1304 = cat(csr__T_1303, csr__T_1296) @[CSR.scala 312:48]
    skip
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    node csr__T_1340 = bits(csr_reg_bp_0_address, 38, 38) @[Package.scala 40:38]
    skip
    node csr__T_1344 = mux(csr__T_1340, UInt<25>("h1ffffff"), UInt<25>("h0")) @[Bitwise.scala 71:12]
    skip
    node csr__T_1345 = cat(csr__T_1344, csr_reg_bp_0_address) @[Cat.scala 30:58]
    node csr__T_1349 = bits(csr_reg_mepc, 39, 39) @[Package.scala 40:38]
    skip
    node csr__T_1353 = mux(csr__T_1349, UInt<24>("hffffff"), UInt<24>("h0")) @[Bitwise.scala 71:12]
    node csr__T_1354 = cat(csr__T_1353, csr_reg_mepc) @[Cat.scala 30:58]
    node csr__T_1355 = bits(csr_reg_mbadaddr, 39, 39) @[Package.scala 40:38]
    skip
    node csr__T_1359 = mux(csr__T_1355, UInt<24>("hffffff"), UInt<24>("h0")) @[Bitwise.scala 71:12]
    node csr__T_1360 = cat(csr__T_1359, csr_reg_mbadaddr) @[Cat.scala 30:58]
    node csr__T_1361 = cat(csr_reg_dcsr_step, csr_reg_dcsr_prv) @[CSR.scala 333:27]
    node csr__T_1362 = cat(UInt<1>("h0"), csr_reg_dcsr_halt) @[CSR.scala 333:27]
    node csr__T_1363 = cat(csr__T_1362, csr__T_1361) @[CSR.scala 333:27]
    node csr__T_1364 = cat(csr_reg_dcsr_cause, csr_reg_dcsr_debugint) @[CSR.scala 333:27]
    skip
    node csr__T_1366 = cat(UInt<2>("h0"), csr__T_1364) @[CSR.scala 333:27]
    node csr__T_1367 = cat(csr__T_1366, csr__T_1363) @[CSR.scala 333:27]
    node csr__T_1368 = cat(csr_reg_dcsr_ebreaku, UInt<1>("h0")) @[CSR.scala 333:27]
    node csr__T_1369 = cat(UInt<1>("h0"), csr_reg_dcsr_ebreaks) @[CSR.scala 333:27]
    node csr__T_1370 = cat(csr__T_1369, csr__T_1368) @[CSR.scala 333:27]
    node csr__T_1371 = cat(UInt<12>("h0"), csr_reg_dcsr_ebreakm) @[CSR.scala 333:27]
    skip
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    node csr__T_1374 = cat(UInt<4>("h4"), csr__T_1371) @[CSR.scala 333:27]
    node csr__T_1375 = cat(csr__T_1374, csr__T_1370) @[CSR.scala 333:27]
    node csr__T_1376 = cat(csr__T_1375, csr__T_1367) @[CSR.scala 333:27]
    node csr__T_1377 = cat(csr_reg_frm, csr_reg_fflags) @[Cat.scala 30:58]
    node csr__T_1380 = and(csr_reg_mie, csr_reg_mideleg) @[CSR.scala 360:28]
    skip
    node csr__T_1381 = and(_GEN_182, csr_reg_mideleg) @[CSR.scala 361:29]
    skip
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    node csr__T_1422 = cat(csr__T_1232, UInt<2>("h0")) @[CSR.scala 371:57]
    node csr__T_1423 = cat(csr__T_1422, csr__T_1230) @[CSR.scala 371:57]
    skip
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    node csr__T_1425 = cat(csr__T_1235, UInt<1>("h0")) @[CSR.scala 371:57]
    skip
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    node csr__T_1426 = cat(csr_reg_mstatus_fs, UInt<2>("h0")) @[CSR.scala 371:57]
    skip
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    node csr__T_1428 = cat(UInt<3>("h0"), csr__T_1426) @[CSR.scala 371:57]
    node csr__T_1429 = cat(csr__T_1428, csr__T_1425) @[CSR.scala 371:57]
    node csr__T_1430 = cat(csr__T_1429, csr__T_1423) @[CSR.scala 371:57]
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    node csr__T_1444 = cat(csr__T_1254, csr__T_1430) @[CSR.scala 371:57]
    node csr__T_1445 = bits(csr__T_1444, 63, 0) @[CSR.scala 371:60]
    node csr__T_1446 = bits(csr_reg_sbadaddr, 39, 39) @[Package.scala 40:38]
    skip
    node csr__T_1450 = mux(csr__T_1446, UInt<24>("hffffff"), UInt<24>("h0")) @[Bitwise.scala 71:12]
    node csr__T_1451 = cat(csr__T_1450, csr_reg_sbadaddr) @[Cat.scala 30:58]
    node csr__T_1452 = cat(csr_reg_sptbr_mode, UInt<16>("h0")) @[CSR.scala 377:45]
    node csr__T_1453 = cat(csr__T_1452, csr_reg_sptbr_ppn) @[CSR.scala 377:45]
    node csr__T_1454 = bits(csr_reg_sepc, 39, 39) @[Package.scala 40:38]
    skip
    node csr__T_1458 = mux(csr__T_1454, UInt<24>("hffffff"), UInt<24>("h0")) @[Bitwise.scala 71:12]
    node csr__T_1459 = cat(csr__T_1458, csr_reg_sepc) @[Cat.scala 30:58]
    node csr__T_1460 = bits(csr_reg_stvec, 38, 38) @[Package.scala 40:38]
    skip
    node csr__T_1464 = mux(csr__T_1460, UInt<25>("h1ffffff"), UInt<25>("h0")) @[Bitwise.scala 71:12]
    node csr__T_1465 = cat(csr__T_1464, csr_reg_stvec) @[Cat.scala 30:58]
    skip
    node csr__T_1469 = eq(csr_io_rw_addr, UInt<12>("h7a1")) @[CSR.scala 405:73]
    node csr__T_1471 = eq(csr_io_rw_addr, UInt<12>("h7a2")) @[CSR.scala 405:73]
    skip
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    node csr__T_1479 = eq(csr_io_rw_addr, UInt<12>("hb00")) @[CSR.scala 405:73]
    node csr__T_1481 = eq(csr_io_rw_addr, UInt<12>("hb02")) @[CSR.scala 405:73]
    node csr__T_1483 = eq(csr_io_rw_addr, UInt<12>("h301")) @[CSR.scala 405:73]
    node csr__T_1485 = eq(csr_io_rw_addr, UInt<12>("h300")) @[CSR.scala 405:73]
    node csr__T_1487 = eq(csr_io_rw_addr, UInt<12>("h305")) @[CSR.scala 405:73]
    node csr__T_1489 = eq(csr_io_rw_addr, UInt<12>("h344")) @[CSR.scala 405:73]
    node csr__T_1491 = eq(csr_io_rw_addr, UInt<12>("h304")) @[CSR.scala 405:73]
    node csr__T_1493 = eq(csr_io_rw_addr, UInt<12>("h303")) @[CSR.scala 405:73]
    node csr__T_1495 = eq(csr_io_rw_addr, UInt<12>("h302")) @[CSR.scala 405:73]
    node csr__T_1497 = eq(csr_io_rw_addr, UInt<12>("h340")) @[CSR.scala 405:73]
    node csr__T_1499 = eq(csr_io_rw_addr, UInt<12>("h341")) @[CSR.scala 405:73]
    node csr__T_1501 = eq(csr_io_rw_addr, UInt<12>("h343")) @[CSR.scala 405:73]
    node csr__T_1503 = eq(csr_io_rw_addr, UInt<12>("h342")) @[CSR.scala 405:73]
    node csr__T_1505 = eq(csr_io_rw_addr, UInt<12>("hf14")) @[CSR.scala 405:73]
    node csr__T_1507 = eq(csr_io_rw_addr, UInt<12>("h7b0")) @[CSR.scala 405:73]
    node csr__T_1509 = eq(csr_io_rw_addr, UInt<12>("h7b1")) @[CSR.scala 405:73]
    node csr__T_1511 = eq(csr_io_rw_addr, UInt<12>("h7b2")) @[CSR.scala 405:73]
    node csr__T_1513 = eq(csr_io_rw_addr, UInt<12>("h1")) @[CSR.scala 405:73]
    node csr__T_1515 = eq(csr_io_rw_addr, UInt<12>("h2")) @[CSR.scala 405:73]
    node csr__T_1517 = eq(csr_io_rw_addr, UInt<12>("h3")) @[CSR.scala 405:73]
    skip
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    node csr__T_1693 = eq(csr_io_rw_addr, UInt<12>("h100")) @[CSR.scala 405:73]
    node csr__T_1695 = eq(csr_io_rw_addr, UInt<12>("h144")) @[CSR.scala 405:73]
    node csr__T_1697 = eq(csr_io_rw_addr, UInt<12>("h104")) @[CSR.scala 405:73]
    node csr__T_1699 = eq(csr_io_rw_addr, UInt<12>("h140")) @[CSR.scala 405:73]
    node csr__T_1701 = eq(csr_io_rw_addr, UInt<12>("h142")) @[CSR.scala 405:73]
    node csr__T_1703 = eq(csr_io_rw_addr, UInt<12>("h143")) @[CSR.scala 405:73]
    node csr__T_1705 = eq(csr_io_rw_addr, UInt<12>("h180")) @[CSR.scala 405:73]
    node csr__T_1707 = eq(csr_io_rw_addr, UInt<12>("h141")) @[CSR.scala 405:73]
    node csr__T_1709 = eq(csr_io_rw_addr, UInt<12>("h105")) @[CSR.scala 405:73]
    node csr__T_1711 = eq(csr_io_rw_addr, UInt<12>("h106")) @[CSR.scala 405:73]
    node csr__T_1713 = eq(csr_io_rw_addr, UInt<12>("h306")) @[CSR.scala 405:73]
    node csr__T_1715 = eq(csr_io_rw_addr, UInt<12>("hc00")) @[CSR.scala 405:73]
    node csr__T_1717 = eq(csr_io_rw_addr, UInt<12>("hc02")) @[CSR.scala 405:73]
    node csr__T_1720 = eq(csr_io_rw_cmd, UInt<3>("h2")) @[Package.scala 7:47]
    node csr__T_1721 = eq(csr_io_rw_cmd, UInt<3>("h3")) @[Package.scala 7:47]
    node csr__T_1722 = or(csr__T_1720, csr__T_1721) @[Package.scala 7:62]
    skip
    node csr__T_2485 = mux(csr__T_1469, csr__T_1304, UInt<64>("h0")) @[Mux.scala 19:72]
    skip
    node csr__T_2487 = mux(csr__T_1471, csr__T_1345, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2736 = or(csr__T_2485, csr__T_2487) @[Mux.scala 19:72]
    skip
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    node csr__T_2495 = mux(csr__T_1479, csr__T_950, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2740 = or(csr__T_2736, csr__T_2495) @[Mux.scala 19:72]
    node csr__T_2497 = mux(csr__T_1481, csr__T_939, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2741 = or(csr__T_2740, csr__T_2497) @[Mux.scala 19:72]
    node csr__T_2499 = mux(csr__T_1483, csr_reg_misa, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2742 = or(csr__T_2741, csr__T_2499) @[Mux.scala 19:72]
    node csr__T_2501 = mux(csr__T_1485, csr_read_mstatus, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2743 = or(csr__T_2742, csr__T_2501) @[Mux.scala 19:72]
    node csr__T_2503 = mux(csr__T_1487, csr_reg_mtvec, UInt<32>("h0")) @[Mux.scala 19:72]
    node _GEN_205 = pad(csr__T_2503, 64) @[Mux.scala 19:72]
    node csr__T_2744 = or(csr__T_2743, _GEN_205) @[Mux.scala 19:72]
    node csr__T_2505 = mux(csr__T_1489, csr_read_mip, UInt<13>("h0")) @[Mux.scala 19:72]
    node _GEN_206 = pad(csr__T_2505, 64) @[Mux.scala 19:72]
    node csr__T_2745 = or(csr__T_2744, _GEN_206) @[Mux.scala 19:72]
    node csr__T_2507 = mux(csr__T_1491, csr_reg_mie, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2746 = or(csr__T_2745, csr__T_2507) @[Mux.scala 19:72]
    node csr__T_2509 = mux(csr__T_1493, csr_reg_mideleg, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2747 = or(csr__T_2746, csr__T_2509) @[Mux.scala 19:72]
    node csr__T_2511 = mux(csr__T_1495, csr_reg_medeleg, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2748 = or(csr__T_2747, csr__T_2511) @[Mux.scala 19:72]
    node csr__T_2513 = mux(csr__T_1497, csr_reg_mscratch, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2749 = or(csr__T_2748, csr__T_2513) @[Mux.scala 19:72]
    node csr__T_2515 = mux(csr__T_1499, csr__T_1354, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2750 = or(csr__T_2749, csr__T_2515) @[Mux.scala 19:72]
    node csr__T_2517 = mux(csr__T_1501, csr__T_1360, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2751 = or(csr__T_2750, csr__T_2517) @[Mux.scala 19:72]
    node csr__T_2519 = mux(csr__T_1503, csr_reg_mcause, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2752 = or(csr__T_2751, csr__T_2519) @[Mux.scala 19:72]
    skip
    node csr__T_2521 = mux(csr__T_1505, io_hartid, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2753 = or(csr__T_2752, csr__T_2521) @[Mux.scala 19:72]
    node csr__T_2523 = mux(csr__T_1507, csr__T_1376, UInt<32>("h0")) @[Mux.scala 19:72]
    node _GEN_207 = pad(csr__T_2523, 64) @[Mux.scala 19:72]
    node csr__T_2754 = or(csr__T_2753, _GEN_207) @[Mux.scala 19:72]
    node csr__T_2525 = mux(csr__T_1509, csr_reg_dpc, UInt<40>("h0")) @[Mux.scala 19:72]
    node _GEN_208 = pad(csr__T_2525, 64) @[Mux.scala 19:72]
    node csr__T_2755 = or(csr__T_2754, _GEN_208) @[Mux.scala 19:72]
    node csr__T_2527 = mux(csr__T_1511, csr_reg_dscratch, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2756 = or(csr__T_2755, csr__T_2527) @[Mux.scala 19:72]
    node csr__T_2529 = mux(csr__T_1513, csr_reg_fflags, UInt<5>("h0")) @[Mux.scala 19:72]
    node _GEN_209 = pad(csr__T_2529, 64) @[Mux.scala 19:72]
    node csr__T_2757 = or(csr__T_2756, _GEN_209) @[Mux.scala 19:72]
    node csr__T_2531 = mux(csr__T_1515, csr_reg_frm, UInt<3>("h0")) @[Mux.scala 19:72]
    node _GEN_210 = pad(csr__T_2531, 64) @[Mux.scala 19:72]
    node csr__T_2758 = or(csr__T_2757, _GEN_210) @[Mux.scala 19:72]
    node csr__T_2533 = mux(csr__T_1517, csr__T_1377, UInt<8>("h0")) @[Mux.scala 19:72]
    node _GEN_211 = pad(csr__T_2533, 64) @[Mux.scala 19:72]
    node csr__T_2759 = or(csr__T_2758, _GEN_211) @[Mux.scala 19:72]
    skip
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    node csr__T_2709 = mux(csr__T_1693, csr__T_1445, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2847 = or(csr__T_2759, csr__T_2709) @[Mux.scala 19:72]
    node csr__T_2711 = mux(csr__T_1695, csr__T_1381, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2848 = or(csr__T_2847, csr__T_2711) @[Mux.scala 19:72]
    node csr__T_2713 = mux(csr__T_1697, csr__T_1380, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2849 = or(csr__T_2848, csr__T_2713) @[Mux.scala 19:72]
    node csr__T_2715 = mux(csr__T_1699, csr_reg_sscratch, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2850 = or(csr__T_2849, csr__T_2715) @[Mux.scala 19:72]
    node csr__T_2717 = mux(csr__T_1701, csr_reg_scause, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2851 = or(csr__T_2850, csr__T_2717) @[Mux.scala 19:72]
    node csr__T_2719 = mux(csr__T_1703, csr__T_1451, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2852 = or(csr__T_2851, csr__T_2719) @[Mux.scala 19:72]
    node csr__T_2721 = mux(csr__T_1705, csr__T_1453, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2853 = or(csr__T_2852, csr__T_2721) @[Mux.scala 19:72]
    node csr__T_2723 = mux(csr__T_1707, csr__T_1459, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2854 = or(csr__T_2853, csr__T_2723) @[Mux.scala 19:72]
    node csr__T_2725 = mux(csr__T_1709, csr__T_1465, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2855 = or(csr__T_2854, csr__T_2725) @[Mux.scala 19:72]
    node csr__T_2727 = mux(csr__T_1711, csr_reg_scounteren, UInt<32>("h0")) @[Mux.scala 19:72]
    node _GEN_212 = pad(csr__T_2727, 64) @[Mux.scala 19:72]
    node csr__T_2856 = or(csr__T_2855, _GEN_212) @[Mux.scala 19:72]
    node csr__T_2729 = mux(csr__T_1713, csr_reg_mcounteren, UInt<32>("h0")) @[Mux.scala 19:72]
    node _GEN_213 = pad(csr__T_2729, 64) @[Mux.scala 19:72]
    node csr__T_2857 = or(csr__T_2856, _GEN_213) @[Mux.scala 19:72]
    node csr__T_2731 = mux(csr__T_1715, csr__T_950, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2858 = or(csr__T_2857, csr__T_2731) @[Mux.scala 19:72]
    node csr__T_2733 = mux(csr__T_1717, csr__T_939, UInt<64>("h0")) @[Mux.scala 19:72]
    node csr__T_2859 = or(csr__T_2858, csr__T_2733) @[Mux.scala 19:72]
    skip
    skip
    node csr__T_1724 = mux(csr__T_1722, csr__T_2859, UInt<64>("h0")) @[CSR.scala 406:19]
    reg wb_reg_wdata : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), wb_reg_wdata) @[Rocket.scala 156:25]
    skip
    node csr__T_1725 = or(csr__T_1724, wb_reg_wdata) @[CSR.scala 406:75]
    skip
    node csr__T_1729 = mux(csr__T_1721, wb_reg_wdata, UInt<64>("h0")) @[CSR.scala 407:19]
    node csr__T_1730 = not(csr__T_1729) @[CSR.scala 407:15]
    node csr_wdata = and(csr__T_1725, csr__T_1730) @[CSR.scala 406:90]
    node csr__T_1740 = bits(csr_opcode, 5, 5) @[CSR.scala 415:39]
    node csr_insn_wfi = and(csr_system_insn, csr__T_1740) @[CSR.scala 415:30]
    skip
    node csr__T_1743 = gt(csr_effective_prv, UInt<3>("h1")) @[CSR.scala 418:51]
    skip
    node csr__T_1746 = not(csr_reg_mstatus_tw) @[CSR.scala 418:62]
    node csr_allow_wfi = or(csr__T_1743, csr__T_1746) @[CSR.scala 418:59]
    skip
    skip
    node csr__T_1752 = not(csr_reg_mstatus_tvm) @[CSR.scala 419:69]
    node csr_allow_sfence_vma = or(csr__T_1743, csr__T_1752) @[CSR.scala 419:66]
    skip
    skip
    node csr__T_1758 = not(csr_reg_mstatus_tsr) @[CSR.scala 420:63]
    node csr_allow_sret = or(csr__T_1743, csr__T_1758) @[CSR.scala 420:60]
    node csr__T_1760 = eq(csr_reg_mstatus_fs, UInt<2>("h0")) @[CSR.scala 421:40]
    node csr__T_1761 = bits(csr_reg_misa, 5, 5) @[CSR.scala 421:58]
    node csr__T_1763 = not(csr__T_1761) @[CSR.scala 421:49]
    node csr__T_1764 = or(csr__T_1760, csr__T_1763) @[CSR.scala 421:46]
    skip
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    node csr_io_decode_csr = bits(ibuf_inst, 31, 20) @[Rocket.scala 461:48]
    skip
    node csr__T_1771 = bits(csr_io_decode_csr, 9, 8) @[CSR.scala 423:58]
    node _GEN_214 = pad(csr__T_1771, 3) @[CSR.scala 423:43]
    node csr__T_1772 = lt(csr_effective_prv, _GEN_214) @[CSR.scala 423:43]
    node csr__T_1774 = eq(csr_io_decode_csr, UInt<12>("h7a0")) @[CSR.scala 424:42]
    node csr__T_1776 = eq(csr_io_decode_csr, UInt<12>("h7a1")) @[CSR.scala 424:42]
    node csr__T_1778 = eq(csr_io_decode_csr, UInt<12>("h7a2")) @[CSR.scala 424:42]
    node csr__T_1780 = eq(csr_io_decode_csr, UInt<12>("hf13")) @[CSR.scala 424:42]
    node csr__T_1782 = eq(csr_io_decode_csr, UInt<12>("hf12")) @[CSR.scala 424:42]
    node csr__T_1784 = eq(csr_io_decode_csr, UInt<12>("hf11")) @[CSR.scala 424:42]
    node csr__T_1786 = eq(csr_io_decode_csr, UInt<12>("hb00")) @[CSR.scala 424:42]
    node csr__T_1788 = eq(csr_io_decode_csr, UInt<12>("hb02")) @[CSR.scala 424:42]
    node csr__T_1790 = eq(csr_io_decode_csr, UInt<12>("h301")) @[CSR.scala 424:42]
    node csr__T_1792 = eq(csr_io_decode_csr, UInt<12>("h300")) @[CSR.scala 424:42]
    node csr__T_1794 = eq(csr_io_decode_csr, UInt<12>("h305")) @[CSR.scala 424:42]
    node csr__T_1796 = eq(csr_io_decode_csr, UInt<12>("h344")) @[CSR.scala 424:42]
    node csr__T_1798 = eq(csr_io_decode_csr, UInt<12>("h304")) @[CSR.scala 424:42]
    node csr__T_1800 = eq(csr_io_decode_csr, UInt<12>("h303")) @[CSR.scala 424:42]
    node csr__T_1802 = eq(csr_io_decode_csr, UInt<12>("h302")) @[CSR.scala 424:42]
    node csr__T_1804 = eq(csr_io_decode_csr, UInt<12>("h340")) @[CSR.scala 424:42]
    node csr__T_1806 = eq(csr_io_decode_csr, UInt<12>("h341")) @[CSR.scala 424:42]
    node csr__T_1808 = eq(csr_io_decode_csr, UInt<12>("h343")) @[CSR.scala 424:42]
    node csr__T_1810 = eq(csr_io_decode_csr, UInt<12>("h342")) @[CSR.scala 424:42]
    node csr__T_1812 = eq(csr_io_decode_csr, UInt<12>("hf14")) @[CSR.scala 424:42]
    node csr__T_1814 = eq(csr_io_decode_csr, UInt<12>("h7b0")) @[CSR.scala 424:42]
    node csr__T_1816 = eq(csr_io_decode_csr, UInt<12>("h7b1")) @[CSR.scala 424:42]
    node csr__T_1818 = eq(csr_io_decode_csr, UInt<12>("h7b2")) @[CSR.scala 424:42]
    node csr__T_1820 = eq(csr_io_decode_csr, UInt<12>("h1")) @[CSR.scala 424:42]
    node csr__T_1822 = eq(csr_io_decode_csr, UInt<12>("h2")) @[CSR.scala 424:42]
    node csr__T_1824 = eq(csr_io_decode_csr, UInt<12>("h3")) @[CSR.scala 424:42]
    node csr__T_1826 = eq(csr_io_decode_csr, UInt<12>("h323")) @[CSR.scala 424:42]
    node csr__T_1828 = eq(csr_io_decode_csr, UInt<12>("hb03")) @[CSR.scala 424:42]
    node csr__T_1830 = eq(csr_io_decode_csr, UInt<12>("hc03")) @[CSR.scala 424:42]
    node csr__T_1832 = eq(csr_io_decode_csr, UInt<12>("h324")) @[CSR.scala 424:42]
    node csr__T_1834 = eq(csr_io_decode_csr, UInt<12>("hb04")) @[CSR.scala 424:42]
    node csr__T_1836 = eq(csr_io_decode_csr, UInt<12>("hc04")) @[CSR.scala 424:42]
    node csr__T_1838 = eq(csr_io_decode_csr, UInt<12>("h325")) @[CSR.scala 424:42]
    node csr__T_1840 = eq(csr_io_decode_csr, UInt<12>("hb05")) @[CSR.scala 424:42]
    node csr__T_1842 = eq(csr_io_decode_csr, UInt<12>("hc05")) @[CSR.scala 424:42]
    node csr__T_1844 = eq(csr_io_decode_csr, UInt<12>("h326")) @[CSR.scala 424:42]
    node csr__T_1846 = eq(csr_io_decode_csr, UInt<12>("hb06")) @[CSR.scala 424:42]
    node csr__T_1848 = eq(csr_io_decode_csr, UInt<12>("hc06")) @[CSR.scala 424:42]
    node csr__T_1850 = eq(csr_io_decode_csr, UInt<12>("h327")) @[CSR.scala 424:42]
    node csr__T_1852 = eq(csr_io_decode_csr, UInt<12>("hb07")) @[CSR.scala 424:42]
    node csr__T_1854 = eq(csr_io_decode_csr, UInt<12>("hc07")) @[CSR.scala 424:42]
    node csr__T_1856 = eq(csr_io_decode_csr, UInt<12>("h328")) @[CSR.scala 424:42]
    node csr__T_1858 = eq(csr_io_decode_csr, UInt<12>("hb08")) @[CSR.scala 424:42]
    node csr__T_1860 = eq(csr_io_decode_csr, UInt<12>("hc08")) @[CSR.scala 424:42]
    node csr__T_1862 = eq(csr_io_decode_csr, UInt<12>("h329")) @[CSR.scala 424:42]
    node csr__T_1864 = eq(csr_io_decode_csr, UInt<12>("hb09")) @[CSR.scala 424:42]
    node csr__T_1866 = eq(csr_io_decode_csr, UInt<12>("hc09")) @[CSR.scala 424:42]
    node csr__T_1868 = eq(csr_io_decode_csr, UInt<12>("h32a")) @[CSR.scala 424:42]
    node csr__T_1870 = eq(csr_io_decode_csr, UInt<12>("hb0a")) @[CSR.scala 424:42]
    node csr__T_1872 = eq(csr_io_decode_csr, UInt<12>("hc0a")) @[CSR.scala 424:42]
    node csr__T_1874 = eq(csr_io_decode_csr, UInt<12>("h32b")) @[CSR.scala 424:42]
    node csr__T_1876 = eq(csr_io_decode_csr, UInt<12>("hb0b")) @[CSR.scala 424:42]
    node csr__T_1878 = eq(csr_io_decode_csr, UInt<12>("hc0b")) @[CSR.scala 424:42]
    node csr__T_1880 = eq(csr_io_decode_csr, UInt<12>("h32c")) @[CSR.scala 424:42]
    node csr__T_1882 = eq(csr_io_decode_csr, UInt<12>("hb0c")) @[CSR.scala 424:42]
    node csr__T_1884 = eq(csr_io_decode_csr, UInt<12>("hc0c")) @[CSR.scala 424:42]
    node csr__T_1886 = eq(csr_io_decode_csr, UInt<12>("h32d")) @[CSR.scala 424:42]
    node csr__T_1888 = eq(csr_io_decode_csr, UInt<12>("hb0d")) @[CSR.scala 424:42]
    node csr__T_1890 = eq(csr_io_decode_csr, UInt<12>("hc0d")) @[CSR.scala 424:42]
    node csr__T_1892 = eq(csr_io_decode_csr, UInt<12>("h32e")) @[CSR.scala 424:42]
    node csr__T_1894 = eq(csr_io_decode_csr, UInt<12>("hb0e")) @[CSR.scala 424:42]
    node csr__T_1896 = eq(csr_io_decode_csr, UInt<12>("hc0e")) @[CSR.scala 424:42]
    node csr__T_1898 = eq(csr_io_decode_csr, UInt<12>("h32f")) @[CSR.scala 424:42]
    node csr__T_1900 = eq(csr_io_decode_csr, UInt<12>("hb0f")) @[CSR.scala 424:42]
    node csr__T_1902 = eq(csr_io_decode_csr, UInt<12>("hc0f")) @[CSR.scala 424:42]
    node csr__T_1904 = eq(csr_io_decode_csr, UInt<12>("h330")) @[CSR.scala 424:42]
    node csr__T_1906 = eq(csr_io_decode_csr, UInt<12>("hb10")) @[CSR.scala 424:42]
    node csr__T_1908 = eq(csr_io_decode_csr, UInt<12>("hc10")) @[CSR.scala 424:42]
    node csr__T_1910 = eq(csr_io_decode_csr, UInt<12>("h331")) @[CSR.scala 424:42]
    node csr__T_1912 = eq(csr_io_decode_csr, UInt<12>("hb11")) @[CSR.scala 424:42]
    node csr__T_1914 = eq(csr_io_decode_csr, UInt<12>("hc11")) @[CSR.scala 424:42]
    node csr__T_1916 = eq(csr_io_decode_csr, UInt<12>("h332")) @[CSR.scala 424:42]
    node csr__T_1918 = eq(csr_io_decode_csr, UInt<12>("hb12")) @[CSR.scala 424:42]
    node csr__T_1920 = eq(csr_io_decode_csr, UInt<12>("hc12")) @[CSR.scala 424:42]
    node csr__T_1922 = eq(csr_io_decode_csr, UInt<12>("h333")) @[CSR.scala 424:42]
    node csr__T_1924 = eq(csr_io_decode_csr, UInt<12>("hb13")) @[CSR.scala 424:42]
    node csr__T_1926 = eq(csr_io_decode_csr, UInt<12>("hc13")) @[CSR.scala 424:42]
    node csr__T_1928 = eq(csr_io_decode_csr, UInt<12>("h334")) @[CSR.scala 424:42]
    node csr__T_1930 = eq(csr_io_decode_csr, UInt<12>("hb14")) @[CSR.scala 424:42]
    node csr__T_1932 = eq(csr_io_decode_csr, UInt<12>("hc14")) @[CSR.scala 424:42]
    node csr__T_1934 = eq(csr_io_decode_csr, UInt<12>("h335")) @[CSR.scala 424:42]
    node csr__T_1936 = eq(csr_io_decode_csr, UInt<12>("hb15")) @[CSR.scala 424:42]
    node csr__T_1938 = eq(csr_io_decode_csr, UInt<12>("hc15")) @[CSR.scala 424:42]
    node csr__T_1940 = eq(csr_io_decode_csr, UInt<12>("h336")) @[CSR.scala 424:42]
    node csr__T_1942 = eq(csr_io_decode_csr, UInt<12>("hb16")) @[CSR.scala 424:42]
    node csr__T_1944 = eq(csr_io_decode_csr, UInt<12>("hc16")) @[CSR.scala 424:42]
    node csr__T_1946 = eq(csr_io_decode_csr, UInt<12>("h337")) @[CSR.scala 424:42]
    node csr__T_1948 = eq(csr_io_decode_csr, UInt<12>("hb17")) @[CSR.scala 424:42]
    node csr__T_1950 = eq(csr_io_decode_csr, UInt<12>("hc17")) @[CSR.scala 424:42]
    node csr__T_1952 = eq(csr_io_decode_csr, UInt<12>("h338")) @[CSR.scala 424:42]
    node csr__T_1954 = eq(csr_io_decode_csr, UInt<12>("hb18")) @[CSR.scala 424:42]
    node csr__T_1956 = eq(csr_io_decode_csr, UInt<12>("hc18")) @[CSR.scala 424:42]
    node csr__T_1958 = eq(csr_io_decode_csr, UInt<12>("h339")) @[CSR.scala 424:42]
    node csr__T_1960 = eq(csr_io_decode_csr, UInt<12>("hb19")) @[CSR.scala 424:42]
    node csr__T_1962 = eq(csr_io_decode_csr, UInt<12>("hc19")) @[CSR.scala 424:42]
    node csr__T_1964 = eq(csr_io_decode_csr, UInt<12>("h33a")) @[CSR.scala 424:42]
    node csr__T_1966 = eq(csr_io_decode_csr, UInt<12>("hb1a")) @[CSR.scala 424:42]
    node csr__T_1968 = eq(csr_io_decode_csr, UInt<12>("hc1a")) @[CSR.scala 424:42]
    node csr__T_1970 = eq(csr_io_decode_csr, UInt<12>("h33b")) @[CSR.scala 424:42]
    node csr__T_1972 = eq(csr_io_decode_csr, UInt<12>("hb1b")) @[CSR.scala 424:42]
    node csr__T_1974 = eq(csr_io_decode_csr, UInt<12>("hc1b")) @[CSR.scala 424:42]
    node csr__T_1976 = eq(csr_io_decode_csr, UInt<12>("h33c")) @[CSR.scala 424:42]
    node csr__T_1978 = eq(csr_io_decode_csr, UInt<12>("hb1c")) @[CSR.scala 424:42]
    node csr__T_1980 = eq(csr_io_decode_csr, UInt<12>("hc1c")) @[CSR.scala 424:42]
    node csr__T_1982 = eq(csr_io_decode_csr, UInt<12>("h33d")) @[CSR.scala 424:42]
    node csr__T_1984 = eq(csr_io_decode_csr, UInt<12>("hb1d")) @[CSR.scala 424:42]
    node csr__T_1986 = eq(csr_io_decode_csr, UInt<12>("hc1d")) @[CSR.scala 424:42]
    node csr__T_1988 = eq(csr_io_decode_csr, UInt<12>("h33e")) @[CSR.scala 424:42]
    node csr__T_1990 = eq(csr_io_decode_csr, UInt<12>("hb1e")) @[CSR.scala 424:42]
    node csr__T_1992 = eq(csr_io_decode_csr, UInt<12>("hc1e")) @[CSR.scala 424:42]
    node csr__T_1994 = eq(csr_io_decode_csr, UInt<12>("h33f")) @[CSR.scala 424:42]
    node csr__T_1996 = eq(csr_io_decode_csr, UInt<12>("hb1f")) @[CSR.scala 424:42]
    node csr__T_1998 = eq(csr_io_decode_csr, UInt<12>("hc1f")) @[CSR.scala 424:42]
    node csr__T_2000 = eq(csr_io_decode_csr, UInt<12>("h100")) @[CSR.scala 424:42]
    node csr__T_2002 = eq(csr_io_decode_csr, UInt<12>("h144")) @[CSR.scala 424:42]
    node csr__T_2004 = eq(csr_io_decode_csr, UInt<12>("h104")) @[CSR.scala 424:42]
    node csr__T_2006 = eq(csr_io_decode_csr, UInt<12>("h140")) @[CSR.scala 424:42]
    node csr__T_2008 = eq(csr_io_decode_csr, UInt<12>("h142")) @[CSR.scala 424:42]
    node csr__T_2010 = eq(csr_io_decode_csr, UInt<12>("h143")) @[CSR.scala 424:42]
    node csr__T_2012 = eq(csr_io_decode_csr, UInt<12>("h180")) @[CSR.scala 424:42]
    node csr__T_2014 = eq(csr_io_decode_csr, UInt<12>("h141")) @[CSR.scala 424:42]
    node csr__T_2016 = eq(csr_io_decode_csr, UInt<12>("h105")) @[CSR.scala 424:42]
    node csr__T_2018 = eq(csr_io_decode_csr, UInt<12>("h106")) @[CSR.scala 424:42]
    node csr__T_2020 = eq(csr_io_decode_csr, UInt<12>("h306")) @[CSR.scala 424:42]
    node csr__T_2022 = eq(csr_io_decode_csr, UInt<12>("hc00")) @[CSR.scala 424:42]
    node csr__T_2024 = eq(csr_io_decode_csr, UInt<12>("hc02")) @[CSR.scala 424:42]
    node csr__T_2025 = or(csr__T_1952, csr__T_1820) @[CSR.scala 424:57]
    node csr__T_2026 = or(csr__T_2025, csr__T_1864) @[CSR.scala 424:57]
    node csr__T_2027 = or(csr__T_2026, csr__T_2006) @[CSR.scala 424:57]
    node csr__T_2028 = or(csr__T_2027, csr__T_1978) @[CSR.scala 424:57]
    node csr__T_2029 = or(csr__T_2028, csr__T_1946) @[CSR.scala 424:57]
    node csr__T_2030 = or(csr__T_2029, csr__T_1832) @[CSR.scala 424:57]
    node csr__T_2031 = or(csr__T_2030, csr__T_1800) @[CSR.scala 424:57]
    node csr__T_2032 = or(csr__T_2031, csr__T_2020) @[CSR.scala 424:57]
    node csr__T_2033 = or(csr__T_2032, csr__T_1914) @[CSR.scala 424:57]
    node csr__T_2034 = or(csr__T_2033, csr__T_1876) @[CSR.scala 424:57]
    node csr__T_2035 = or(csr__T_2034, csr__T_1920) @[CSR.scala 424:57]
    node csr__T_2036 = or(csr__T_2035, csr__T_1788) @[CSR.scala 424:57]
    node csr__T_2037 = or(csr__T_2036, csr__T_1844) @[CSR.scala 424:57]
    node csr__T_2038 = or(csr__T_2037, csr__T_1888) @[CSR.scala 424:57]
    node csr__T_2039 = or(csr__T_2038, csr__T_1872) @[CSR.scala 424:57]
    node csr__T_2040 = or(csr__T_2039, csr__T_1988) @[CSR.scala 424:57]
    node csr__T_2041 = or(csr__T_2040, csr__T_1910) @[CSR.scala 424:57]
    node csr__T_2042 = or(csr__T_2041, csr__T_1924) @[CSR.scala 424:57]
    node csr__T_2043 = or(csr__T_2042, csr__T_1776) @[CSR.scala 424:57]
    node csr__T_2044 = or(csr__T_2043, csr__T_1808) @[CSR.scala 424:57]
    node csr__T_2045 = or(csr__T_2044, csr__T_1892) @[CSR.scala 424:57]
    node csr__T_2046 = or(csr__T_2045, csr__T_1840) @[CSR.scala 424:57]
    node csr__T_2047 = or(csr__T_2046, csr__T_1956) @[CSR.scala 424:57]
    node csr__T_2048 = or(csr__T_2047, csr__T_2010) @[CSR.scala 424:57]
    node csr__T_2049 = or(csr__T_2048, csr__T_1868) @[CSR.scala 424:57]
    node csr__T_2050 = or(csr__T_2049, csr__T_2000) @[CSR.scala 424:57]
    node csr__T_2051 = or(csr__T_2050, csr__T_1878) @[CSR.scala 424:57]
    node csr__T_2052 = or(csr__T_2051, csr__T_1942) @[CSR.scala 424:57]
    node csr__T_2053 = or(csr__T_2052, csr__T_1812) @[CSR.scala 424:57]
    node csr__T_2054 = or(csr__T_2053, csr__T_1974) @[CSR.scala 424:57]
    node csr__T_2055 = or(csr__T_2054, csr__T_1968) @[CSR.scala 424:57]
    node csr__T_2056 = or(csr__T_2055, csr__T_1780) @[CSR.scala 424:57]
    node csr__T_2057 = or(csr__T_2056, csr__T_1836) @[CSR.scala 424:57]
    node csr__T_2058 = or(csr__T_2057, csr__T_1996) @[CSR.scala 424:57]
    node csr__T_2059 = or(csr__T_2058, csr__T_1814) @[CSR.scala 424:57]
    node csr__T_2060 = or(csr__T_2059, csr__T_1900) @[CSR.scala 424:57]
    node csr__T_2061 = or(csr__T_2060, csr__T_1846) @[CSR.scala 424:57]
    node csr__T_2062 = or(csr__T_2061, csr__T_1932) @[CSR.scala 424:57]
    node csr__T_2063 = or(csr__T_2062, csr__T_1964) @[CSR.scala 424:57]
    node csr__T_2064 = or(csr__T_2063, csr__T_1782) @[CSR.scala 424:57]
    node csr__T_2065 = or(csr__T_2064, csr__T_1904) @[CSR.scala 424:57]
    node csr__T_2066 = or(csr__T_2065, csr__T_1992) @[CSR.scala 424:57]
    node csr__T_2067 = or(csr__T_2066, csr__T_1860) @[CSR.scala 424:57]
    node csr__T_2068 = or(csr__T_2067, csr__T_1804) @[CSR.scala 424:57]
    node csr__T_2069 = or(csr__T_2068, csr__T_1936) @[CSR.scala 424:57]
    node csr__T_2070 = or(csr__T_2069, csr__T_1960) @[CSR.scala 424:57]
    node csr__T_2071 = or(csr__T_2070, csr__T_1828) @[CSR.scala 424:57]
    node csr__T_2072 = or(csr__T_2071, csr__T_1908) @[CSR.scala 424:57]
    node csr__T_2073 = or(csr__T_2072, csr__T_2024) @[CSR.scala 424:57]
    node csr__T_2074 = or(csr__T_2073, csr__T_2004) @[CSR.scala 424:57]
    node csr__T_2075 = or(csr__T_2074, csr__T_1856) @[CSR.scala 424:57]
    node csr__T_2076 = or(csr__T_2075, csr__T_1940) @[CSR.scala 424:57]
    node csr__T_2077 = or(csr__T_2076, csr__T_1792) @[CSR.scala 424:57]
    node csr__T_2078 = or(csr__T_2077, csr__T_1972) @[CSR.scala 424:57]
    node csr__T_2079 = or(csr__T_2078, csr__T_1824) @[CSR.scala 424:57]
    node csr__T_2080 = or(csr__T_2079, csr__T_1896) @[CSR.scala 424:57]
    node csr__T_2081 = or(csr__T_2080, csr__T_1928) @[CSR.scala 424:57]
    node csr__T_2082 = or(csr__T_2081, csr__T_1796) @[CSR.scala 424:57]
    node csr__T_2083 = or(csr__T_2082, csr__T_1918) @[CSR.scala 424:57]
    node csr__T_2084 = or(csr__T_2083, csr__T_1786) @[CSR.scala 424:57]
    node csr__T_2085 = or(csr__T_2084, csr__T_1980) @[CSR.scala 424:57]
    node csr__T_2086 = or(csr__T_2085, csr__T_1774) @[CSR.scala 424:57]
    node csr__T_2087 = or(csr__T_2086, csr__T_1830) @[CSR.scala 424:57]
    node csr__T_2088 = or(csr__T_2087, csr__T_1890) @[CSR.scala 424:57]
    node csr__T_2089 = or(csr__T_2088, csr__T_2018) @[CSR.scala 424:57]
    node csr__T_2090 = or(csr__T_2089, csr__T_1916) @[CSR.scala 424:57]
    node csr__T_2091 = or(csr__T_2090, csr__T_1884) @[CSR.scala 424:57]
    node csr__T_2092 = or(csr__T_2091, csr__T_1862) @[CSR.scala 424:57]
    node csr__T_2093 = or(csr__T_2092, csr__T_1948) @[CSR.scala 424:57]
    node csr__T_2094 = or(csr__T_2093, csr__T_1798) @[CSR.scala 424:57]
    node csr__T_2095 = or(csr__T_2094, csr__T_1976) @[CSR.scala 424:57]
    node csr__T_2096 = or(csr__T_2095, csr__T_1886) @[CSR.scala 424:57]
    node csr__T_2097 = or(csr__T_2096, csr__T_1950) @[CSR.scala 424:57]
    node csr__T_2098 = or(csr__T_2097, csr__T_1818) @[CSR.scala 424:57]
    node csr__T_2099 = or(csr__T_2098, csr__T_1982) @[CSR.scala 424:57]
    node csr__T_2100 = or(csr__T_2099, csr__T_1850) @[CSR.scala 424:57]
    node csr__T_2101 = or(csr__T_2100, csr__T_1810) @[CSR.scala 424:57]
    node csr__T_2102 = or(csr__T_2101, csr__T_1944) @[CSR.scala 424:57]
    node csr__T_2103 = or(csr__T_2102, csr__T_2014) @[CSR.scala 424:57]
    node csr__T_2104 = or(csr__T_2103, csr__T_1838) @[CSR.scala 424:57]
    node csr__T_2105 = or(csr__T_2104, csr__T_1954) @[CSR.scala 424:57]
    node csr__T_2106 = or(csr__T_2105, csr__T_1870) @[CSR.scala 424:57]
    node csr__T_2107 = or(csr__T_2106, csr__T_1986) @[CSR.scala 424:57]
    node csr__T_2108 = or(csr__T_2107, csr__T_2008) @[CSR.scala 424:57]
    node csr__T_2109 = or(csr__T_2108, csr__T_1922) @[CSR.scala 424:57]
    node csr__T_2110 = or(csr__T_2109, csr__T_1778) @[CSR.scala 424:57]
    node csr__T_2111 = or(csr__T_2110, csr__T_1806) @[CSR.scala 424:57]
    node csr__T_2112 = or(csr__T_2111, csr__T_1842) @[CSR.scala 424:57]
    node csr__T_2113 = or(csr__T_2112, csr__T_1874) @[CSR.scala 424:57]
    node csr__T_2114 = or(csr__T_2113, csr__T_1880) @[CSR.scala 424:57]
    node csr__T_2115 = or(csr__T_2114, csr__T_2012) @[CSR.scala 424:57]
    node csr__T_2116 = or(csr__T_2115, csr__T_1912) @[CSR.scala 424:57]
    node csr__T_2117 = or(csr__T_2116, csr__T_1802) @[CSR.scala 424:57]
    node csr__T_2118 = or(csr__T_2117, csr__T_1934) @[CSR.scala 424:57]
    node csr__T_2119 = or(csr__T_2118, csr__T_1848) @[CSR.scala 424:57]
    node csr__T_2120 = or(csr__T_2119, csr__T_1962) @[CSR.scala 424:57]
    node csr__T_2121 = or(csr__T_2120, csr__T_1784) @[CSR.scala 424:57]
    node csr__T_2122 = or(csr__T_2121, csr__T_1902) @[CSR.scala 424:57]
    node csr__T_2123 = or(csr__T_2122, csr__T_1994) @[CSR.scala 424:57]
    node csr__T_2124 = or(csr__T_2123, csr__T_2016) @[CSR.scala 424:57]
    node csr__T_2125 = or(csr__T_2124, csr__T_1930) @[CSR.scala 424:57]
    node csr__T_2126 = or(csr__T_2125, csr__T_1816) @[CSR.scala 424:57]
    node csr__T_2127 = or(csr__T_2126, csr__T_1834) @[CSR.scala 424:57]
    node csr__T_2128 = or(csr__T_2127, csr__T_1966) @[CSR.scala 424:57]
    node csr__T_2129 = or(csr__T_2128, csr__T_1898) @[CSR.scala 424:57]
    node csr__T_2130 = or(csr__T_2129, csr__T_1866) @[CSR.scala 424:57]
    node csr__T_2131 = or(csr__T_2130, csr__T_1998) @[CSR.scala 424:57]
    node csr__T_2132 = or(csr__T_2131, csr__T_1926) @[CSR.scala 424:57]
    node csr__T_2133 = or(csr__T_2132, csr__T_1794) @[CSR.scala 424:57]
    node csr__T_2134 = or(csr__T_2133, csr__T_1882) @[CSR.scala 424:57]
    node csr__T_2135 = or(csr__T_2134, csr__T_1970) @[CSR.scala 424:57]
    node csr__T_2136 = or(csr__T_2135, csr__T_1822) @[CSR.scala 424:57]
    node csr__T_2137 = or(csr__T_2136, csr__T_1894) @[CSR.scala 424:57]
    node csr__T_2138 = or(csr__T_2137, csr__T_2002) @[CSR.scala 424:57]
    node csr__T_2139 = or(csr__T_2138, csr__T_1854) @[CSR.scala 424:57]
    node csr__T_2140 = or(csr__T_2139, csr__T_1938) @[CSR.scala 424:57]
    node csr__T_2141 = or(csr__T_2140, csr__T_1984) @[CSR.scala 424:57]
    node csr__T_2142 = or(csr__T_2141, csr__T_1790) @[CSR.scala 424:57]
    node csr__T_2143 = or(csr__T_2142, csr__T_1852) @[CSR.scala 424:57]
    node csr__T_2144 = or(csr__T_2143, csr__T_1958) @[CSR.scala 424:57]
    node csr__T_2145 = or(csr__T_2144, csr__T_1826) @[CSR.scala 424:57]
    node csr__T_2146 = or(csr__T_2145, csr__T_2022) @[CSR.scala 424:57]
    node csr__T_2147 = or(csr__T_2146, csr__T_1906) @[CSR.scala 424:57]
    node csr__T_2148 = or(csr__T_2147, csr__T_1990) @[CSR.scala 424:57]
    node csr__T_2149 = or(csr__T_2148, csr__T_1858) @[CSR.scala 424:57]
    node csr__T_2151 = not(csr__T_2149) @[CSR.scala 424:5]
    node csr__T_2152 = or(csr__T_1772, csr__T_2151) @[CSR.scala 423:64]
    skip
    node csr__T_2156 = not(csr_allow_sfence_vma) @[CSR.scala 425:37]
    node csr__T_2157 = and(csr__T_2012, csr__T_2156) @[CSR.scala 425:34]
    node csr__T_2158 = or(csr__T_2152, csr__T_2157) @[CSR.scala 424:62]
    node csr__T_2161 = geq(csr_io_decode_csr, UInt<12>("hc00")) @[Package.scala 47:47]
    node csr__T_2162 = lt(csr_io_decode_csr, UInt<12>("hc20")) @[Package.scala 47:60]
    node csr__T_2163 = and(csr__T_2161, csr__T_2162) @[Package.scala 47:55]
    node csr__T_2166 = geq(csr_io_decode_csr, UInt<12>("hc80")) @[Package.scala 47:47]
    node csr__T_2167 = lt(csr_io_decode_csr, UInt<12>("hca0")) @[Package.scala 47:60]
    node csr__T_2168 = and(csr__T_2166, csr__T_2167) @[Package.scala 47:55]
    node csr__T_2169 = or(csr__T_2163, csr__T_2168) @[CSR.scala 426:67]
    node csr__T_2171 = leq(csr_effective_prv, UInt<3>("h1")) @[CSR.scala 426:151]
    node csr__T_2172 = and(csr__T_2169, csr__T_2171) @[CSR.scala 426:134]
    skip
    node csr__T_2174 = dshr(csr_hpm_mask, csr_io_decode_csr) @[CSR.scala 426:171]
    node csr__T_2175 = bits(csr__T_2174, 0, 0) @[CSR.scala 426:171]
    node csr__T_2176 = and(csr__T_2172, csr__T_2175) @[CSR.scala 426:160]
    node csr__T_2177 = or(csr__T_2158, csr__T_2176) @[CSR.scala 425:55]
    skip
    skip
    skip
    skip
    skip
    node csr__T_2188 = or(csr__T_1814, csr__T_1816) @[CSR.scala 427:88]
    node csr__T_2189 = or(csr__T_2188, csr__T_1818) @[CSR.scala 427:88]
    node csr__T_2190 = and(csr__T_1207, csr__T_2189) @[CSR.scala 427:36]
    node csr__T_2191 = or(csr__T_2177, csr__T_2190) @[CSR.scala 426:215]
    skip
    skip
    skip
    node csr__T_2199 = or(csr__T_1820, csr__T_1822) @[CSR.scala 428:69]
    node csr__T_2200 = or(csr__T_2199, csr__T_1824) @[CSR.scala 428:69]
    skip
    skip
    node csr__T_2202 = and(csr__T_2200, csr__T_1764) @[CSR.scala 428:74]
    node csr__T_2203 = or(csr__T_2191, csr__T_2202) @[CSR.scala 427:93]
    node csr__T_2204 = bits(csr_io_decode_csr, 11, 10) @[CSR.scala 429:43]
    node csr__T_2205 = not(csr__T_2204) @[CSR.scala 429:51]
    node csr__T_2207 = eq(csr__T_2205, UInt<2>("h0")) @[CSR.scala 429:51]
    node csr__T_2209 = geq(csr_io_decode_csr, UInt<12>("h340")) @[CSR.scala 430:44]
    node csr__T_2211 = leq(csr_io_decode_csr, UInt<12>("h343")) @[CSR.scala 430:78]
    node csr__T_2212 = and(csr__T_2209, csr__T_2211) @[CSR.scala 430:61]
    node csr__T_2214 = geq(csr_io_decode_csr, UInt<12>("h140")) @[CSR.scala 430:112]
    node csr__T_2216 = leq(csr_io_decode_csr, UInt<12>("h143")) @[CSR.scala 430:146]
    node csr__T_2217 = and(csr__T_2214, csr__T_2216) @[CSR.scala 430:129]
    node csr__T_2218 = or(csr__T_2212, csr__T_2217) @[CSR.scala 430:95]
    node csr__T_2220 = not(csr__T_2218) @[CSR.scala 430:28]
    skip
    skip
    skip
    node csr__T_2223 = bits(csr_io_decode_csr, 5, 5) @[CSR.scala 432:19]
    node csr__T_2225 = not(csr__T_2223) @[CSR.scala 432:5]
    node csr__T_2226 = bits(csr_io_decode_csr, 2, 2) @[CSR.scala 432:39]
    node csr__T_2227 = and(csr__T_2225, csr__T_2226) @[CSR.scala 432:23]
    node csr__T_2229 = not(csr_allow_wfi) @[CSR.scala 432:46]
    node csr__T_2230 = and(csr__T_2227, csr__T_2229) @[CSR.scala 432:43]
    node csr__T_2231 = or(csr__T_1772, csr__T_2230) @[CSR.scala 431:66]
    skip
    skip
    node csr__T_2235 = bits(csr_io_decode_csr, 1, 1) @[CSR.scala 433:39]
    node csr__T_2236 = and(csr__T_2225, csr__T_2235) @[CSR.scala 433:23]
    node csr__T_2238 = not(csr_allow_sret) @[CSR.scala 433:46]
    node csr__T_2239 = and(csr__T_2236, csr__T_2238) @[CSR.scala 433:43]
    node csr__T_2240 = or(csr__T_2231, csr__T_2239) @[CSR.scala 432:57]
    skip
    skip
    node csr__T_2244 = and(csr__T_2223, csr__T_2156) @[CSR.scala 434:22]
    node csr__T_2245 = or(csr__T_2240, csr__T_2244) @[CSR.scala 433:58]
    node csr_debugTVec = mux(csr_reg_debug, UInt<12>("h808"), UInt<12>("h800")) @[CSR.scala 445:22]
    skip
    node csr__T_2328 = cat(csr__T_1460, csr_reg_stvec) @[Cat.scala 30:58]
    node csr__T_2329 = mux(csr_delegate, csr__T_2328, pad(csr_reg_mtvec, 40)) @[CSR.scala 446:45]
    node csr_tvec = mux(csr__T_2314, pad(csr_debugTVec, 40), csr__T_2329) @[CSR.scala 446:17]
    node csr__T_2345 = add(csr_insn_ret, csr_insn_call) @[Bitwise.scala 48:55]
    node csr__T_2346 = add(csr_insn_break, wb_reg_xcpt) @[Bitwise.scala 48:55]
    node csr__T_2347 = add(csr__T_2345, csr__T_2346) @[Bitwise.scala 48:55]
    node csr__T_2349 = leq(csr__T_2347, UInt<3>("h1")) @[CSR.scala 462:79]
    skip
    node csr__T_2350 = or(csr__T_2349, reset) @[CSR.scala 462:9]
    node csr__T_2352 = not(csr__T_2350) @[CSR.scala 462:9]
    node csr__GEN_36 = or(csr_insn_wfi, csr_reg_wfi) @[CSR.scala 464:19 264:20 464:29]
    node csr__T_2355 = neq(csr_pending_interrupts, UInt<64>("h0")) @[CSR.scala 465:28]
    node csr__T_2356 = or(csr__T_2355, csr_exception) @[CSR.scala 465:32]
    node csr__GEN_37 = mux(csr__T_2356, UInt<1>("h0"), csr__GEN_36) @[CSR.scala 465:{46,56}]
    node csr__T_2359 = not(csr_reg_wfi) @[CSR.scala 466:10]
    node csr__T_2361 = not(wb_valid) @[CSR.scala 466:32]
    node csr__T_2362 = or(csr__T_2359, csr__T_2361) @[CSR.scala 466:19]
    node csr__T_2363 = or(csr__T_2362, reset) @[CSR.scala 466:9]
    node csr__T_2365 = not(csr__T_2363) @[CSR.scala 466:9]
    skip
    node csr__GEN_38 = or(wb_valid, csr_reg_singleStepped) @[CSR.scala 468:23 236:30 468:43]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    node csr__T_2380 = not(csr_reg_singleStepped) @[CSR.scala 471:10]
    skip
    node csr__T_2383 = or(csr__T_2380, csr__T_2361) @[CSR.scala 471:29]
    node csr__T_2384 = or(csr__T_2383, reset) @[CSR.scala 471:9]
    node csr__T_2386 = not(csr__T_2384) @[CSR.scala 471:9]
    reg wb_reg_pc : UInt<40>, const_clock with :
      reset => (UInt<1>("h0"), wb_reg_pc) @[Rocket.scala 154:22]
    skip
    node csr__T_2387 = not(wb_reg_pc) @[CSR.scala 474:17]
    node csr__T_2389 = or(csr__T_2387, UInt<40>("h1")) @[CSR.scala 474:24]
    node csr__T_2390 = not(csr__T_2389) @[CSR.scala 474:15]
    node csr__T_2391 = dshr(csr_read_mstatus, csr_reg_mstatus_prv) @[CSR.scala 475:27]
    node csr__T_2392 = bits(csr__T_2391, 0, 0) @[CSR.scala 475:27]
    node csr__T_2400 = eq(csr_cause, UInt<64>("h3")) @[Package.scala 7:47]
    node csr__T_2401 = eq(csr_cause, UInt<64>("h4")) @[Package.scala 7:47]
    node csr__T_2402 = eq(csr_cause, UInt<64>("h6")) @[Package.scala 7:47]
    node csr__T_2403 = eq(csr_cause, UInt<64>("h0")) @[Package.scala 7:47]
    node csr__T_2404 = eq(csr_cause, UInt<64>("h5")) @[Package.scala 7:47]
    node csr__T_2405 = eq(csr_cause, UInt<64>("h7")) @[Package.scala 7:47]
    node csr__T_2406 = eq(csr_cause, UInt<64>("h1")) @[Package.scala 7:47]
    node csr__T_2407 = or(csr__T_2400, csr__T_2401) @[Package.scala 7:62]
    node csr__T_2408 = or(csr__T_2407, csr__T_2402) @[Package.scala 7:62]
    node csr__T_2409 = or(csr__T_2408, csr__T_2403) @[Package.scala 7:62]
    node csr__T_2410 = or(csr__T_2409, csr__T_2404) @[Package.scala 7:62]
    node csr__T_2411 = or(csr__T_2410, csr__T_2405) @[Package.scala 7:62]
    node csr__T_2412 = or(csr__T_2411, csr__T_2406) @[Package.scala 7:62]
    node csr__T_2418 = mux(csr_causeIsDebugTrigger, UInt<2>("h2"), UInt<2>("h1")) @[CSR.scala 484:84]
    node csr__T_2419 = mux(csr_causeIsDebugInt, UInt<2>("h3"), csr__T_2418) @[CSR.scala 484:54]
    node csr__T_2420 = mux(csr_reg_singleStepped, UInt<3>("h4"), pad(csr__T_2419, 3)) @[CSR.scala 484:28]
    node csr__GEN_40 = or(csr__T_2314, csr_reg_debug) @[CSR.scala 481:24 482:17 232:22]
    node csr__GEN_41 = mux(csr__T_2314, csr__T_2390, csr_reg_dpc) @[CSR.scala 481:24 483:15 234:20]
    node csr__GEN_42 = mux(csr__T_2314, csr__T_2420, csr_reg_dcsr_cause) @[CSR.scala 205:21 481:24 484:22]
    node csr__GEN_43 = mux(csr__T_2314, csr_reg_mstatus_prv, csr_reg_dcsr_prv) @[CSR.scala 481:24 485:20 205:21]
    node csr__T_2424 = not(csr__T_2390) @[CSR.scala 714:28]
    node csr__T_2425 = bits(csr_reg_misa, 2, 2) @[CSR.scala 714:46]
    node csr__T_2427 = not(csr__T_2425) @[CSR.scala 714:37]
    node csr__T_2429 = cat(csr__T_2427, UInt<1>("h1")) @[Cat.scala 30:58]
    node _GEN_216 = pad(csr__T_2429, 40) @[CSR.scala 714:31]
    node csr__T_2430 = or(csr__T_2424, _GEN_216) @[CSR.scala 714:31]
    node csr__T_2431 = not(csr__T_2430) @[CSR.scala 714:26]
    node _T_4204 = shr(wb_reg_wdata, 38) @[Rocket.scala 653:16]
    node _T_4208 = eq(_T_4204, UInt<26>("h0")) @[Rocket.scala 656:13]
    node _T_4210 = eq(_T_4204, UInt<26>("h1")) @[Rocket.scala 656:30]
    node _T_4211 = or(_T_4208, _T_4210) @[Rocket.scala 656:25]
    node _T_4205 = bits(wb_reg_wdata, 39, 38) @[Rocket.scala 654:15]
    node _T_4206 = asSInt(_T_4205) @[Rocket.scala 654:39]
    node _T_4213 = neq(_T_4206, SInt<2>("h0")) @[Rocket.scala 656:45]
    node _T_4214 = asSInt(_T_4204) @[Rocket.scala 657:13]
    node _T_4216 = eq(_T_4214, SInt<26>("h-1")) @[Rocket.scala 657:20]
    skip
    node _T_4219 = eq(_T_4214, SInt<26>("h-2")) @[Rocket.scala 657:45]
    node _T_4220 = or(_T_4216, _T_4219) @[Rocket.scala 657:33]
    node _T_4222 = eq(_T_4206, SInt<2>("h-1")) @[Rocket.scala 657:61]
    node _T_4223 = bits(_T_4206, 0, 0) @[Rocket.scala 657:76]
    node _T_4224 = mux(_T_4220, _T_4222, _T_4223) @[Rocket.scala 657:10]
    node _T_4225 = mux(_T_4211, _T_4213, _T_4224) @[Rocket.scala 656:10]
    node _T_4226 = bits(wb_reg_wdata, 38, 0) @[Rocket.scala 658:16]
    node csr_io_badaddr = cat(_T_4225, _T_4226) @[Cat.scala 30:58]
    skip
    node csr__GEN_44 = mux(csr__T_2412, csr_io_badaddr, csr_reg_sbadaddr) @[CSR.scala 260:25 489:{28,43}]
    node csr__GEN_45 = mux(csr__T_2423, csr__T_2431, csr_reg_sepc) @[CSR.scala 486:27 487:16 258:21]
    node csr__GEN_46 = mux(csr__T_2423, csr_cause, csr_reg_scause) @[CSR.scala 486:27 488:18 259:23]
    node csr__GEN_47 = mux(csr__T_2423, csr__GEN_44, csr_reg_sbadaddr) @[CSR.scala 260:25 486:27]
    node csr__GEN_48 = mux(csr__T_2423, csr__T_2392, csr_reg_mstatus_spie) @[CSR.scala 197:24 486:27 490:24]
    node csr__GEN_49 = mux(csr__T_2423, csr_reg_mstatus_prv, pad(csr_reg_mstatus_spp, 2)) @[CSR.scala 486:27 491:23 197:24]
    node csr__GEN_50 = mux(csr__T_2423, UInt<1>("h0"), csr_reg_mstatus_sie) @[CSR.scala 486:27 492:23 197:24]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    node csr__GEN_52 = mux(csr__T_2412, csr_io_badaddr, csr_reg_mbadaddr) @[CSR.scala 247:25 497:{28,43}]
    node csr__GEN_53 = mux(csr__T_2438, csr__T_2431, csr_reg_mepc) @[CSR.scala 494:17 495:16 245:21]
    node csr__GEN_54 = mux(csr__T_2438, csr_cause, csr_reg_mcause) @[CSR.scala 494:17 496:18 246:23]
    node csr__GEN_55 = mux(csr__T_2438, csr__GEN_52, csr_reg_mbadaddr) @[CSR.scala 494:17 247:25]
    node csr__GEN_56 = mux(csr__T_2438, csr__T_2392, csr_reg_mstatus_mpie) @[CSR.scala 494:17 197:24 498:24]
    node csr__GEN_57 = mux(csr__T_2438, csr_reg_mstatus_prv, csr_reg_mstatus_mpp) @[CSR.scala 494:17 499:23 197:24]
    node csr__GEN_58 = mux(csr__T_2438, UInt<1>("h0"), csr_reg_mstatus_mie) @[CSR.scala 494:17 500:23 197:24]
    node csr__GEN_60 = mux(csr_exception, csr__GEN_40, csr_reg_debug) @[CSR.scala 473:20 232:22]
    node csr__GEN_61 = mux(csr_exception, csr__GEN_41, csr_reg_dpc) @[CSR.scala 234:20 473:20]
    node csr__GEN_62 = mux(csr_exception, csr__GEN_42, csr_reg_dcsr_cause) @[CSR.scala 473:20 205:21]
    node csr__GEN_63 = mux(csr_exception, csr__GEN_43, csr_reg_dcsr_prv) @[CSR.scala 473:20 205:21]
    node csr__GEN_64 = mux(csr_exception, csr__GEN_45, csr_reg_sepc) @[CSR.scala 473:20 258:21]
    node csr__GEN_65 = mux(csr_exception, csr__GEN_46, csr_reg_scause) @[CSR.scala 473:20 259:23]
    node csr__GEN_66 = mux(csr_exception, csr__GEN_47, csr_reg_sbadaddr) @[CSR.scala 473:20 260:25]
    node csr__GEN_67 = mux(csr_exception, csr__GEN_48, csr_reg_mstatus_spie) @[CSR.scala 473:20 197:24]
    node csr__GEN_68 = mux(csr_exception, csr__GEN_49, pad(csr_reg_mstatus_spp, 2)) @[CSR.scala 473:20 197:24]
    node csr__GEN_69 = mux(csr_exception, csr__GEN_50, csr_reg_mstatus_sie) @[CSR.scala 473:20 197:24]
    node csr__GEN_71 = mux(csr_exception, csr__GEN_53, csr_reg_mepc) @[CSR.scala 473:20 245:21]
    node csr__GEN_72 = mux(csr_exception, csr__GEN_54, csr_reg_mcause) @[CSR.scala 473:20 246:23]
    node csr__GEN_73 = mux(csr_exception, csr__GEN_55, csr_reg_mbadaddr) @[CSR.scala 473:20 247:25]
    node csr__GEN_74 = mux(csr_exception, csr__GEN_56, csr_reg_mstatus_mpie) @[CSR.scala 473:20 197:24]
    node csr__GEN_75 = mux(csr_exception, csr__GEN_57, csr_reg_mstatus_mpp) @[CSR.scala 473:20 197:24]
    node csr__GEN_76 = mux(csr_exception, csr__GEN_58, csr_reg_mstatus_mie) @[CSR.scala 473:20 197:24]
    skip
    node csr__GEN_77 = mux(csr_reg_mstatus_spp, csr_reg_mstatus_spie, csr__GEN_69) @[CSR.scala 507:{37,55}]
    node csr__GEN_78 = mux(csr__T_2452, csr__GEN_77, csr__GEN_69) @[CSR.scala 506:44]
    node csr__GEN_79 = or(csr__T_2452, csr__GEN_67) @[CSR.scala 506:44 508:24]
    node csr__GEN_80 = mux(csr__T_2452, UInt<2>("h0"), csr__GEN_68) @[CSR.scala 506:44 509:23]
    node csr__GEN_82 = mux(csr__T_2452, csr_reg_sepc, csr_tvec) @[CSR.scala 448:11 506:44 511:15]
    node csr__GEN_84 = mux(csr__T_2462, UInt<1>("h0"), csr__GEN_60) @[CSR.scala 512:53 514:17]
    node csr__GEN_85 = mux(csr__T_2462, csr_reg_dpc, csr__GEN_82) @[CSR.scala 512:53 515:15]
    node csr__T_2469 = bits(csr_reg_mstatus_mpp, 1, 1) @[CSR.scala 517:28]
    node csr__GEN_86 = mux(csr__T_2469, csr_reg_mstatus_mpie, csr__GEN_76) @[CSR.scala 517:{33,51}]
    node csr__T_2471 = bits(csr_reg_mstatus_mpp, 0, 0) @[CSR.scala 518:50]
    skip
    node csr__T_2474 = not(csr__T_2469) @[CSR.scala 517:33]
    node csr__T_2475 = and(csr__T_2474, csr__T_2471) @[CSR.scala 518:55]
    node csr__GEN_87 = mux(csr__T_2475, csr_reg_mstatus_mpie, csr__GEN_78) @[CSR.scala 518:{55,73}]
    skip
    skip
    node csr__GEN_88 = mux(csr__T_2468, csr__GEN_86, csr__GEN_76) @[CSR.scala 516:17]
    node csr__GEN_89 = mux(csr__T_2468, csr__GEN_87, csr__GEN_78) @[CSR.scala 516:17]
    node csr__GEN_90 = or(csr__T_2468, csr__GEN_74) @[CSR.scala 516:17 519:24]
    node csr__GEN_91 = mux(csr__T_2468, UInt<2>("h0"), csr__GEN_75) @[CSR.scala 516:17 520:23]
    node csr__GEN_93 = mux(csr__T_2468, csr_reg_mepc, csr__GEN_85) @[CSR.scala 516:17 522:15]
    node csr__GEN_94 = mux(csr_insn_ret, csr__GEN_89, csr__GEN_69) @[CSR.scala 505:19]
    node csr__GEN_95 = mux(csr_insn_ret, csr__GEN_79, csr__GEN_67) @[CSR.scala 505:19]
    node csr__GEN_96 = mux(csr_insn_ret, csr__GEN_80, csr__GEN_68) @[CSR.scala 505:19]
    node csr__GEN_98 = mux(csr_insn_ret, csr__GEN_93, csr_tvec) @[CSR.scala 448:11 505:19]
    node csr__GEN_99 = mux(csr_insn_ret, csr__GEN_84, csr__GEN_60) @[CSR.scala 505:19]
    node csr__GEN_100 = mux(csr_insn_ret, csr__GEN_88, csr__GEN_76) @[CSR.scala 505:19]
    node csr__GEN_101 = mux(csr_insn_ret, csr__GEN_90, csr__GEN_74) @[CSR.scala 505:19]
    node csr__GEN_102 = mux(csr_insn_ret, csr__GEN_91, csr__GEN_75) @[CSR.scala 505:19]
    skip
    node csr__T_2862 = or(csr_reg_fflags, io_fpu_fcsr_flags_bits) @[CSR.scala 533:30]
    skip
    node csr__GEN_103 = mux(io_fpu_fcsr_flags_valid, csr__T_2862, csr_reg_fflags) @[CSR.scala 532:30 533:16 266:23]
    skip
    skip
    node csr__T_2868 = eq(csr_io_rw_cmd, UInt<3>("h1")) @[Package.scala 7:47]
    skip
    node csr__T_2870 = or(csr__T_1722, csr__T_2868) @[Package.scala 7:62]
    node csr__T_2959 = pad(csr_wdata, 99)
    skip
    node csr__T_2961 = bits(csr__T_2959, 1, 1) @[CSR.scala 538:47]
    skip
    node csr__T_2963 = bits(csr__T_2959, 3, 3) @[CSR.scala 538:47]
    skip
    node csr__T_2965 = bits(csr__T_2959, 5, 5) @[CSR.scala 538:47]
    skip
    node csr__T_2967 = bits(csr__T_2959, 7, 7) @[CSR.scala 538:47]
    node csr__T_2968 = bits(csr__T_2959, 8, 8) @[CSR.scala 538:47]
    skip
    node csr__T_2970 = bits(csr__T_2959, 12, 11) @[CSR.scala 538:47]
    node csr__T_2971 = bits(csr__T_2959, 14, 13) @[CSR.scala 538:47]
    skip
    node csr__T_2973 = bits(csr__T_2959, 17, 17) @[CSR.scala 538:47]
    node csr__T_2974 = bits(csr__T_2959, 18, 18) @[CSR.scala 538:47]
    node csr__T_2975 = bits(csr__T_2959, 19, 19) @[CSR.scala 538:47]
    node csr__T_2976 = bits(csr__T_2959, 20, 20) @[CSR.scala 538:47]
    node csr__T_2977 = bits(csr__T_2959, 21, 21) @[CSR.scala 538:47]
    node csr__T_2978 = bits(csr__T_2959, 22, 22) @[CSR.scala 538:47]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    node csr__T_2989 = neq(csr__T_2971, UInt<2>("h0")) @[CSR.scala 557:73]
    skip
    node csr__T_2993 = mux(csr__T_2989, UInt<2>("h3"), UInt<2>("h0")) @[Bitwise.scala 71:12]
    skip
    node csr__GEN_104 = mux(csr__T_1485, csr__T_2963, csr__GEN_100) @[CSR.scala 537:39 539:23]
    skip
    node csr__GEN_105 = mux(csr__T_1485, csr__T_2967, csr__GEN_101) @[CSR.scala 537:39 540:24]
    skip
    node csr__GEN_106 = mux(csr__T_1485, csr__T_2973, csr_reg_mstatus_mprv) @[CSR.scala 197:24 537:39 543:26]
    skip
    node csr__GEN_107 = mux(csr__T_1485, csr__T_2970, csr__GEN_102) @[CSR.scala 537:39 544:25]
    skip
    node csr__GEN_108 = mux(csr__T_1485, csr__T_2975, csr_reg_mstatus_mxr) @[CSR.scala 197:24 537:39 545:25]
    skip
    node csr__GEN_109 = mux(csr__T_1485, csr__T_2974, csr_reg_mstatus_pum) @[CSR.scala 197:24 537:39 547:27]
    skip
    node csr__GEN_110 = mux(csr__T_1485, pad(csr__T_2968, 2), csr__GEN_96) @[CSR.scala 537:39 548:27]
    skip
    node csr__GEN_111 = mux(csr__T_1485, csr__T_2965, csr__GEN_95) @[CSR.scala 537:39 549:28]
    skip
    node csr__GEN_112 = mux(csr__T_1485, csr__T_2961, csr__GEN_94) @[CSR.scala 537:39 550:27]
    skip
    node csr__GEN_113 = mux(csr__T_1485, csr__T_2977, csr_reg_mstatus_tw) @[CSR.scala 197:24 537:39 551:26]
    skip
    node csr__GEN_114 = mux(csr__T_1485, csr__T_2976, csr_reg_mstatus_tvm) @[CSR.scala 197:24 537:39 552:27]
    skip
    node csr__GEN_115 = mux(csr__T_1485, csr__T_2978, csr_reg_mstatus_tsr) @[CSR.scala 197:24 537:39 553:27]
    node csr__GEN_116 = mux(csr__T_1485, csr__T_2993, csr_reg_mstatus_fs) @[CSR.scala 197:24 537:39 557:47]
    node csr__T_2995 = bits(csr_wdata, 5, 5) @[CSR.scala 562:20]
    node csr__T_2996 = not(csr_wdata) @[CSR.scala 563:21]
    node csr__T_2998 = not(csr__T_2995) @[CSR.scala 563:31]
    node csr__T_2999 = shl(csr__T_2998, 3) @[CSR.scala 563:34]
    node _GEN_218 = pad(csr__T_2999, 64) @[CSR.scala 563:28]
    node csr__T_3000 = or(csr__T_2996, _GEN_218) @[CSR.scala 563:28]
    node csr__T_3001 = not(csr__T_3000) @[CSR.scala 563:19]
    node csr__T_3002 = and(csr__T_3001, UInt<64>("h102d")) @[CSR.scala 563:51]
    skip
    node csr__T_3004 = and(csr_reg_misa, UInt<64>("hfd2")) @[CSR.scala 563:69]
    node csr__T_3005 = or(csr__T_3002, csr__T_3004) @[CSR.scala 563:58]
    node csr__GEN_117 = mux(csr__T_1483, csr__T_3005, csr_reg_misa) @[CSR.scala 560:36 563:16 307:21]
    node csr__T_3049 = bits(csr_wdata, 12, 0)
    skip
    node csr__T_3051 = bits(csr__T_3049, 1, 1) @[CSR.scala 566:39]
    skip
    skip
    skip
    node csr__T_3055 = bits(csr__T_3049, 5, 5) @[CSR.scala 566:39]
    skip
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    skip
    node csr__GEN_118 = mux(csr__T_1489, csr__T_3051, csr_reg_mip_ssip) @[CSR.scala 244:20 565:35 568:22]
    skip
    node csr__GEN_119 = mux(csr__T_1489, csr__T_3055, csr_reg_mip_stip) @[CSR.scala 244:20 565:35 569:22]
    node csr__T_3063 = and(csr_wdata, UInt<64>("haaa")) @[CSR.scala 572:59]
    node csr__GEN_120 = mux(csr__T_1491, csr__T_3063, csr_reg_mie) @[CSR.scala 241:20 572:{40,50}]
    skip
    skip
    skip
    skip
    node _GEN_219 = pad(csr__T_2429, 64) @[CSR.scala 714:31]
    node csr__T_3070 = or(csr__T_2996, _GEN_219) @[CSR.scala 714:31]
    node csr__T_3071 = not(csr__T_3070) @[CSR.scala 714:26]
    node csr__GEN_121 = mux(csr__T_1499, csr__T_3071, pad(csr__GEN_71, 64)) @[CSR.scala 573:{40,51}]
    node csr__GEN_122 = mux(csr__T_1497, csr_wdata, csr_reg_mscratch) @[CSR.scala 248:25 574:{40,55}]
    node csr__T_3072 = shr(csr_wdata, 2) @[CSR.scala 576:61]
    node csr__T_3073 = shl(csr__T_3072, 2) @[CSR.scala 576:66]
    node csr__GEN_123 = mux(csr__T_1487, csr__T_3073, pad(csr_reg_mtvec, 64)) @[CSR.scala 251:27 576:{40,52}]
    node csr__T_3075 = and(csr_wdata, UInt<64>("h800000000000001f")) @[CSR.scala 577:62]
    node csr__GEN_124 = mux(csr__T_1503, csr__T_3075, csr__GEN_72) @[CSR.scala 577:{40,53}]
    node csr__T_3076 = bits(csr_wdata, 39, 0) @[CSR.scala 578:63]
    node csr__GEN_125 = mux(csr__T_1501, csr__T_3076, csr__GEN_73) @[CSR.scala 578:{40,55}]
    skip
    node csr__T_3078 = shr(csr_wdata, 6) @[Counters.scala 68:28]
    node csr__GEN_126 = mux(csr__T_1479, csr_wdata, pad(csr__T_943, 64)) @[CSR.scala 711:31 Counters.scala 67:11 49:9]
    node csr__GEN_127 = mux(csr__T_1479, csr__T_3078, csr__GEN_1) @[CSR.scala 711:31 Counters.scala 68:23]
    skip
    skip
    node csr__GEN_128 = mux(csr__T_1481, csr_wdata, pad(csr__T_932, 64)) @[CSR.scala 711:31 Counters.scala 67:11 49:9]
    node csr__GEN_129 = mux(csr__T_1481, csr__T_3078, csr__GEN_0) @[CSR.scala 711:31 Counters.scala 68:23]
    node csr__GEN_130 = mux(csr__T_1513, csr_wdata, pad(csr__GEN_103, 64)) @[CSR.scala 588:{40,53}]
    node csr__GEN_131 = mux(csr__T_1515, csr_wdata, pad(csr_reg_frm, 64)) @[CSR.scala 267:20 589:{40,50}]
    node csr__T_3081 = shr(csr_wdata, 5) @[CSR.scala 590:80]
    node csr__GEN_132 = mux(csr__T_1517, csr_wdata, csr__GEN_130) @[CSR.scala 590:{40,53}]
    node csr__GEN_133 = mux(csr__T_1517, pad(csr__T_3081, 64), csr__GEN_131) @[CSR.scala 590:{40,71}]
    node csr__T_3137 = bits(csr_wdata, 31, 0)
    node csr__T_3138 = bits(csr__T_3137, 1, 0) @[CSR.scala 594:43]
    node csr__T_3139 = bits(csr__T_3137, 2, 2) @[CSR.scala 594:43]
    node csr__T_3140 = bits(csr__T_3137, 3, 3) @[CSR.scala 594:43]
    skip
    skip
    skip
    skip
    skip
    skip
    node csr__T_3147 = bits(csr__T_3137, 12, 12) @[CSR.scala 594:43]
    node csr__T_3148 = bits(csr__T_3137, 13, 13) @[CSR.scala 594:43]
    skip
    node csr__T_3150 = bits(csr__T_3137, 15, 15) @[CSR.scala 594:43]
    skip
    skip
    skip
    skip
    skip
    node csr__GEN_134 = mux(csr__T_1507, csr__T_3140, csr_reg_dcsr_halt) @[CSR.scala 205:21 593:38 595:23]
    skip
    node csr__GEN_135 = mux(csr__T_1507, csr__T_3139, csr_reg_dcsr_step) @[CSR.scala 205:21 593:38 596:23]
    skip
    node csr__GEN_136 = mux(csr__T_1507, csr__T_3150, csr_reg_dcsr_ebreakm) @[CSR.scala 205:21 593:38 597:26]
    skip
    node csr__GEN_137 = mux(csr__T_1507, csr__T_3148, csr_reg_dcsr_ebreaks) @[CSR.scala 205:21 593:38 598:39]
    skip
    node csr__GEN_138 = mux(csr__T_1507, csr__T_3147, csr_reg_dcsr_ebreaku) @[CSR.scala 205:21 593:38 599:41]
    skip
    node csr__GEN_139 = mux(csr__T_1507, csr__T_3138, csr__GEN_63) @[CSR.scala 593:38 600:37]
    skip
    node csr__T_3157 = or(csr__T_2996, UInt<64>("h1")) @[CSR.scala 602:64]
    node csr__T_3158 = not(csr__T_3157) @[CSR.scala 602:55]
    node csr__GEN_140 = mux(csr__T_1509, csr__T_3158, pad(csr__GEN_61, 64)) @[CSR.scala 602:{42,52}]
    node csr__GEN_141 = mux(csr__T_1511, csr_wdata, csr_reg_dscratch) @[CSR.scala 235:25 603:{42,57}]
    skip
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    node csr__GEN_142 = mux(csr__T_1693, csr__T_2961, csr__GEN_112) @[CSR.scala 606:41 608:25]
    skip
    node csr__GEN_143 = mux(csr__T_1693, csr__T_2965, csr__GEN_111) @[CSR.scala 606:41 609:26]
    skip
    node csr__GEN_144 = mux(csr__T_1693, pad(csr__T_2968, 2), csr__GEN_110) @[CSR.scala 606:41 610:25]
    skip
    node csr__GEN_145 = mux(csr__T_1693, csr__T_2974, csr__GEN_109) @[CSR.scala 606:41 611:25]
    node csr__GEN_146 = mux(csr__T_1693, csr__T_2993, csr__GEN_116) @[CSR.scala 606:41 612:24]
    skip
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    node csr__GEN_147 = mux(csr__T_1695, csr__T_3051, csr__GEN_118) @[CSR.scala 615:37 617:22]
    skip
    node csr__T_3353 = bits(csr_wdata, 43, 0) @[CSR.scala 620:44]
    skip
    node csr__T_3355 = bits(csr_wdata, 63, 60) @[CSR.scala 620:44]
    skip
    node csr__T_3357 = eq(csr__T_3355, UInt<4>("h0")) @[CSR.scala 622:30]
    node csr__GEN_148 = mux(csr__T_3357, UInt<4>("h0"), csr_reg_sptbr_mode) @[CSR.scala 263:22 622:{37,54}]
    node csr__T_3360 = eq(csr__T_3355, UInt<4>("h8")) @[CSR.scala 623:30]
    node csr__GEN_149 = mux(csr__T_3360, UInt<4>("h8"), csr__GEN_148) @[CSR.scala 623:{46,63}]
    skip
    skip
    node csr__T_3366 = or(csr__T_3357, csr__T_3360) @[CSR.scala 624:36]
    skip
    node csr__T_3367 = bits(csr__T_3353, 19, 0) @[CSR.scala 625:41]
    node csr__GEN_150 = mux(csr__T_3366, pad(csr__T_3367, 44), csr_reg_sptbr_ppn) @[CSR.scala 263:22 624:70 625:25]
    node csr__GEN_151 = mux(csr__T_1705, csr__GEN_149, csr_reg_sptbr_mode) @[CSR.scala 263:22 619:39]
    node csr__GEN_152 = mux(csr__T_1705, csr__GEN_150, csr_reg_sptbr_ppn) @[CSR.scala 263:22 619:39]
    skip
    node csr__T_3369 = and(csr_reg_mie, csr__T_988) @[CSR.scala 629:64]
    node csr__T_3370 = and(csr_wdata, csr_reg_mideleg) @[CSR.scala 629:89]
    node csr__T_3371 = or(csr__T_3369, csr__T_3370) @[CSR.scala 629:80]
    node csr__GEN_153 = mux(csr__T_1697, csr__T_3371, csr__GEN_120) @[CSR.scala 629:{42,52}]
    node csr__GEN_154 = mux(csr__T_1699, csr_wdata, csr_reg_sscratch) @[CSR.scala 261:25 630:{42,57}]
    skip
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    node csr__GEN_155 = mux(csr__T_1707, csr__T_3071, pad(csr__GEN_64, 64)) @[CSR.scala 631:{42,53}]
    skip
    skip
    node csr__GEN_156 = mux(csr__T_1709, csr__T_3073, pad(csr_reg_stvec, 64)) @[CSR.scala 262:22 632:{42,54}]
    skip
    node csr__GEN_157 = mux(csr__T_1701, csr__T_3075, csr__GEN_65) @[CSR.scala 633:{42,55}]
    skip
    node csr__GEN_158 = mux(csr__T_1703, csr__T_3076, csr__GEN_66) @[CSR.scala 634:{42,57}]
    node csr__T_3385 = and(csr_wdata, UInt<64>("h222")) @[CSR.scala 635:65]
    node csr__GEN_159 = mux(csr__T_1493, csr__T_3385, csr_reg_mideleg) @[CSR.scala 242:24 635:{42,56}]
    node csr__T_3386 = and(csr_wdata, UInt<64>("h1ab")) @[CSR.scala 636:65]
    node csr__GEN_160 = mux(csr__T_1495, csr__T_3386, csr_reg_medeleg) @[CSR.scala 243:24 636:{42,56}]
    node csr__T_3388 = and(csr_wdata, UInt<64>("h7")) @[CSR.scala 637:70]
    node csr__GEN_161 = mux(csr__T_1711, csr__T_3388, pad(csr_reg_scounteren, 64)) @[CSR.scala 255:27 637:{44,61}]
    skip
    node csr__GEN_162 = mux(csr__T_1713, csr__T_3388, pad(csr_reg_mcounteren, 64)) @[CSR.scala 254:27 640:{44,61}]
    skip
    skip
    node csr__T_3427 = not(csr_reg_bp_0_control_dmode) @[CSR.scala 646:13]
    node csr__T_3428 = or(csr__T_3427, csr_reg_debug) @[CSR.scala 646:31]
    skip
    node csr__T_3479 = bits(csr_wdata, 0, 0) @[CSR.scala 648:48]
    node csr__T_3480 = bits(csr_wdata, 1, 1) @[CSR.scala 648:48]
    node csr__T_3481 = bits(csr_wdata, 2, 2) @[CSR.scala 648:48]
    node csr__T_3482 = bits(csr_wdata, 3, 3) @[CSR.scala 648:48]
    node csr__T_3483 = bits(csr_wdata, 4, 4) @[CSR.scala 648:48]
    skip
    node csr__T_3485 = bits(csr_wdata, 6, 6) @[CSR.scala 648:48]
    node csr__T_3486 = bits(csr_wdata, 8, 7) @[CSR.scala 648:48]
    skip
    skip
    node csr__T_3489 = bits(csr_wdata, 12, 12) @[CSR.scala 648:48]
    skip
    skip
    node csr__T_3492 = bits(csr_wdata, 59, 59) @[CSR.scala 648:48]
    skip
    skip
    node csr__T_3494 = and(csr__T_3492, csr_reg_debug) @[CSR.scala 649:36]
    skip
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    node csr__T_3495 = and(csr__T_3494, csr__T_3489) @[CSR.scala 652:38]
    skip
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    node csr__GEN_200 = mux(csr__T_1469, csr__T_3494, csr_reg_bp_0_control_dmode) @[CSR.scala 239:19 647:42]
    skip
    skip
    skip
    skip
    skip
    node csr__GEN_206 = mux(csr__T_1469, csr__T_3495, csr_reg_bp_0_control_action) @[CSR.scala 239:19 647:42]
    skip
    skip
    skip
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    skip
    node csr__GEN_212 = mux(csr__T_1469, csr__T_3486, csr_reg_bp_0_control_tmatch) @[CSR.scala 239:19 647:42]
    skip
    node csr__GEN_214 = mux(csr__T_1469, csr__T_3485, csr_reg_bp_0_control_m) @[CSR.scala 239:19 647:42]
    skip
    skip
    skip
    node csr__GEN_218 = mux(csr__T_1469, csr__T_3483, csr_reg_bp_0_control_s) @[CSR.scala 239:19 647:42]
    skip
    node csr__GEN_220 = mux(csr__T_1469, csr__T_3482, csr_reg_bp_0_control_u) @[CSR.scala 239:19 647:42]
    skip
    node csr__GEN_222 = mux(csr__T_1469, csr__T_3481, csr_reg_bp_0_control_x) @[CSR.scala 239:19 647:42]
    skip
    node csr__GEN_224 = mux(csr__T_1469, csr__T_3480, csr_reg_bp_0_control_w) @[CSR.scala 239:19 647:42]
    skip
    node csr__GEN_226 = mux(csr__T_1469, csr__T_3479, csr_reg_bp_0_control_r) @[CSR.scala 239:19 647:42]
    skip
    node csr__reg_bp_reg_tselect_address_1 = bits(csr_wdata, 38, 0) @[CSR.scala 654:{55,55}]
    skip
    skip
    node csr__GEN_230 = mux(csr__T_1471, csr__reg_bp_reg_tselect_address_1, csr_reg_bp_0_address) @[CSR.scala 239:19 654:42]
    skip
    skip
    skip
    node csr__GEN_234 = mux(csr__T_3428, csr__GEN_200, csr_reg_bp_0_control_dmode) @[CSR.scala 239:19 646:45]
    skip
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    node csr__GEN_240 = mux(csr__T_3428, csr__GEN_206, csr_reg_bp_0_control_action) @[CSR.scala 239:19 646:45]
    skip
    skip
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    node csr__GEN_246 = mux(csr__T_3428, csr__GEN_212, csr_reg_bp_0_control_tmatch) @[CSR.scala 239:19 646:45]
    skip
    node csr__GEN_248 = mux(csr__T_3428, csr__GEN_214, csr_reg_bp_0_control_m) @[CSR.scala 239:19 646:45]
    skip
    skip
    skip
    node csr__GEN_252 = mux(csr__T_3428, csr__GEN_218, csr_reg_bp_0_control_s) @[CSR.scala 239:19 646:45]
    skip
    node csr__GEN_254 = mux(csr__T_3428, csr__GEN_220, csr_reg_bp_0_control_u) @[CSR.scala 239:19 646:45]
    skip
    node csr__GEN_256 = mux(csr__T_3428, csr__GEN_222, csr_reg_bp_0_control_x) @[CSR.scala 239:19 646:45]
    skip
    node csr__GEN_258 = mux(csr__T_3428, csr__GEN_224, csr_reg_bp_0_control_w) @[CSR.scala 239:19 646:45]
    skip
    node csr__GEN_260 = mux(csr__T_3428, csr__GEN_226, csr_reg_bp_0_control_r) @[CSR.scala 239:19 646:45]
    skip
    node csr__GEN_262 = mux(csr__T_3428, csr__GEN_230, csr_reg_bp_0_address) @[CSR.scala 239:19 646:45]
    skip
    node csr__GEN_264 = mux(csr__T_2870, csr__GEN_104, csr__GEN_100) @[CSR.scala 536:49]
    node csr__GEN_265 = mux(csr__T_2870, csr__GEN_105, csr__GEN_101) @[CSR.scala 536:49]
    node csr__GEN_266 = mux(csr__T_2870, csr__GEN_106, csr_reg_mstatus_mprv) @[CSR.scala 197:24 536:49]
    node csr__GEN_267 = mux(csr__T_2870, csr__GEN_107, csr__GEN_102) @[CSR.scala 536:49]
    node csr__GEN_268 = mux(csr__T_2870, csr__GEN_108, csr_reg_mstatus_mxr) @[CSR.scala 197:24 536:49]
    node csr__GEN_269 = mux(csr__T_2870, csr__GEN_145, csr_reg_mstatus_pum) @[CSR.scala 197:24 536:49]
    node csr__GEN_270 = mux(csr__T_2870, csr__GEN_144, csr__GEN_96) @[CSR.scala 536:49]
    node csr__GEN_271 = mux(csr__T_2870, csr__GEN_143, csr__GEN_95) @[CSR.scala 536:49]
    node csr__GEN_272 = mux(csr__T_2870, csr__GEN_142, csr__GEN_94) @[CSR.scala 536:49]
    node csr__GEN_273 = mux(csr__T_2870, csr__GEN_113, csr_reg_mstatus_tw) @[CSR.scala 197:24 536:49]
    node csr__GEN_274 = mux(csr__T_2870, csr__GEN_114, csr_reg_mstatus_tvm) @[CSR.scala 197:24 536:49]
    node csr__GEN_275 = mux(csr__T_2870, csr__GEN_115, csr_reg_mstatus_tsr) @[CSR.scala 197:24 536:49]
    node csr__GEN_276 = mux(csr__T_2870, csr__GEN_146, csr_reg_mstatus_fs) @[CSR.scala 197:24 536:49]
    node csr__GEN_277 = mux(csr__T_2870, csr__GEN_117, csr_reg_misa) @[CSR.scala 307:21 536:49]
    skip
    skip
    skip
    node csr__GEN_281 = mux(csr__T_2870, csr__GEN_121, pad(csr__GEN_71, 64)) @[CSR.scala 536:49]
    skip
    node csr__GEN_283 = mux(csr__T_2870, csr__GEN_123, pad(csr_reg_mtvec, 64)) @[CSR.scala 251:27 536:49]
    skip
    skip
    node csr__GEN_286 = mux(csr__T_2870, csr__GEN_126, pad(csr__T_943, 64)) @[CSR.scala 536:49 Counters.scala 49:9]
    node csr__GEN_287 = mux(csr__T_2870, csr__GEN_127, csr__GEN_1) @[CSR.scala 536:49]
    node csr__GEN_288 = mux(csr__T_2870, csr__GEN_128, pad(csr__T_932, 64)) @[CSR.scala 536:49 Counters.scala 49:9]
    node csr__GEN_289 = mux(csr__T_2870, csr__GEN_129, csr__GEN_0) @[CSR.scala 536:49]
    node csr__GEN_290 = mux(csr__T_2870, csr__GEN_132, pad(csr__GEN_103, 64)) @[CSR.scala 536:49]
    node csr__GEN_291 = mux(csr__T_2870, csr__GEN_133, pad(csr_reg_frm, 64)) @[CSR.scala 267:20 536:49]
    node csr__GEN_292 = mux(csr__T_2870, csr__GEN_134, csr_reg_dcsr_halt) @[CSR.scala 205:21 536:49]
    node csr__GEN_293 = mux(csr__T_2870, csr__GEN_135, csr_reg_dcsr_step) @[CSR.scala 205:21 536:49]
    node csr__GEN_294 = mux(csr__T_2870, csr__GEN_136, csr_reg_dcsr_ebreakm) @[CSR.scala 205:21 536:49]
    node csr__GEN_295 = mux(csr__T_2870, csr__GEN_137, csr_reg_dcsr_ebreaks) @[CSR.scala 205:21 536:49]
    node csr__GEN_296 = mux(csr__T_2870, csr__GEN_138, csr_reg_dcsr_ebreaku) @[CSR.scala 205:21 536:49]
    node csr__GEN_297 = mux(csr__T_2870, csr__GEN_139, csr__GEN_63) @[CSR.scala 536:49]
    node csr__GEN_298 = mux(csr__T_2870, csr__GEN_140, pad(csr__GEN_61, 64)) @[CSR.scala 536:49]
    skip
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    node csr__GEN_303 = mux(csr__T_2870, csr__GEN_155, pad(csr__GEN_64, 64)) @[CSR.scala 536:49]
    node csr__GEN_304 = mux(csr__T_2870, csr__GEN_156, pad(csr_reg_stvec, 64)) @[CSR.scala 262:22 536:49]
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    node csr__GEN_309 = mux(csr__T_2870, csr__GEN_161, pad(csr_reg_scounteren, 64)) @[CSR.scala 255:27 536:49]
    node csr__GEN_310 = mux(csr__T_2870, csr__GEN_162, pad(csr_reg_mcounteren, 64)) @[CSR.scala 254:27 536:49]
    skip
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    node csr__GEN_314 = mux(csr__T_2870, csr__GEN_234, csr_reg_bp_0_control_dmode) @[CSR.scala 239:19 536:49]
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    node csr__GEN_320 = mux(csr__T_2870, csr__GEN_240, csr_reg_bp_0_control_action) @[CSR.scala 239:19 536:49]
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    node csr__GEN_336 = mux(csr__T_2870, csr__GEN_256, csr_reg_bp_0_control_x) @[CSR.scala 239:19 536:49]
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    node csr__GEN_338 = mux(csr__T_2870, csr__GEN_258, csr_reg_bp_0_control_w) @[CSR.scala 239:19 536:49]
    skip
    node csr__GEN_340 = mux(csr__T_2870, csr__GEN_260, csr_reg_bp_0_control_r) @[CSR.scala 239:19 536:49]
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    node bpu__T_216 = dshr(csr__T_1295, csr_reg_mstatus_prv) @[Breakpoint.scala 30:68]
    node bpu__T_217 = bits(bpu__T_216, 0, 0) @[Breakpoint.scala 30:68]
    node bpu__T_218 = and(csr__T_1207, bpu__T_217) @[Breakpoint.scala 30:50]
    skip
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    node bpu__T_220 = and(bpu__T_218, csr_reg_bp_0_control_r) @[Breakpoint.scala 73:22]
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    node bpu__T_221 = bits(csr_reg_bp_0_control_tmatch, 1, 1) @[Breakpoint.scala 47:23]
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    node bpu__T_222 = geq(_T_4023, csr_reg_bp_0_address) @[Breakpoint.scala 44:8]
    node bpu__T_223 = bits(csr_reg_bp_0_control_tmatch, 0, 0) @[Breakpoint.scala 44:36]
    node bpu__T_224 = xor(bpu__T_222, bpu__T_223) @[Breakpoint.scala 44:20]
    node bpu__T_225 = not(_T_4023) @[Breakpoint.scala 41:6]
    skip
    node bpu__T_227 = bits(csr_reg_bp_0_address, 0, 0) @[Breakpoint.scala 38:83]
    node bpu__T_228 = and(bpu__T_223, bpu__T_227) @[Breakpoint.scala 38:73]
    node bpu__T_229 = bits(csr_reg_bp_0_address, 1, 1) @[Breakpoint.scala 38:83]
    node bpu__T_230 = and(bpu__T_228, bpu__T_229) @[Breakpoint.scala 38:73]
    node bpu__T_231 = bits(csr_reg_bp_0_address, 2, 2) @[Breakpoint.scala 38:83]
    node bpu__T_232 = and(bpu__T_230, bpu__T_231) @[Breakpoint.scala 38:73]
    node bpu__T_233 = cat(bpu__T_228, bpu__T_223) @[Cat.scala 30:58]
    node bpu__T_234 = cat(bpu__T_232, bpu__T_230) @[Cat.scala 30:58]
    node bpu__T_235 = cat(bpu__T_234, bpu__T_233) @[Cat.scala 30:58]
    node _GEN_221 = pad(bpu__T_235, 39) @[Breakpoint.scala 41:9]
    node bpu__T_236 = or(bpu__T_225, _GEN_221) @[Breakpoint.scala 41:9]
    node bpu__T_237 = not(csr_reg_bp_0_address) @[Breakpoint.scala 41:24]
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    node bpu__T_248 = or(bpu__T_237, _GEN_221) @[Breakpoint.scala 41:33]
    node bpu__T_249 = eq(bpu__T_236, bpu__T_248) @[Breakpoint.scala 41:19]
    node bpu__T_250 = mux(bpu__T_221, bpu__T_224, bpu__T_249) @[Breakpoint.scala 47:8]
    node bpu__T_251 = and(bpu__T_220, bpu__T_250) @[Breakpoint.scala 73:38]
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    node bpu__T_253 = and(bpu__T_218, csr_reg_bp_0_control_w) @[Breakpoint.scala 74:22]
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    node bpu__T_284 = and(bpu__T_253, bpu__T_250) @[Breakpoint.scala 74:38]
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    node bpu__T_286 = and(bpu__T_218, csr_reg_bp_0_control_x) @[Breakpoint.scala 75:22]
    skip
    node bpu_io_pc = bits(ibuf__T_512, 38, 0)
    node bpu__T_288 = geq(bpu_io_pc, csr_reg_bp_0_address) @[Breakpoint.scala 44:8]
    skip
    node bpu__T_290 = xor(bpu__T_288, bpu__T_223) @[Breakpoint.scala 44:20]
    node bpu__T_291 = not(bpu_io_pc) @[Breakpoint.scala 41:6]
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    node bpu__T_302 = or(bpu__T_291, _GEN_221) @[Breakpoint.scala 41:9]
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    node bpu__T_315 = eq(bpu__T_302, bpu__T_248) @[Breakpoint.scala 41:19]
    node bpu__T_316 = mux(bpu__T_221, bpu__T_290, bpu__T_315) @[Breakpoint.scala 47:8]
    node bpu__T_317 = and(bpu__T_286, bpu__T_316) @[Breakpoint.scala 75:38]
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    node bpu__T_322 = not(csr_reg_bp_0_control_action) @[Breakpoint.scala 78:37]
    node bpu__GEN_0 = and(bpu__T_251, bpu__T_322) @[Breakpoint.scala 65:14 78:{21,34}]
    node bpu__GEN_1 = and(bpu__T_251, csr_reg_bp_0_control_action) @[Breakpoint.scala 68:15 78:{21,69}]
    skip
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    node bpu__GEN_2 = and(bpu__T_284, bpu__T_322) @[Breakpoint.scala 66:14 79:{21,34}]
    node bpu__GEN_3 = and(bpu__T_284, csr_reg_bp_0_control_action) @[Breakpoint.scala 69:15 79:{21,69}]
    skip
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    node bpu__GEN_4 = and(bpu__T_317, bpu__T_322) @[Breakpoint.scala 64:14 80:{21,34}]
    node bpu__GEN_5 = and(bpu__T_317, csr_reg_bp_0_control_action) @[Breakpoint.scala 67:15 80:{21,69}]
    skip
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    reg ex_ctrl_alu_fn : UInt<4>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_alu_fn) @[Rocket.scala 115:20]
    skip
    node alu__T_16 = bits(ex_ctrl_alu_fn, 3, 3) @[ALU.scala 41:29]
    reg ex_ctrl_sel_alu2 : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_sel_alu2) @[Rocket.scala 115:20]
    node _T_3711 = eq(UInt<2>("h2"), ex_ctrl_sel_alu2) @[Mux.scala 46:19]
    reg ex_reg_rs_bypass_1 : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_rs_bypass_1) @[Rocket.scala 247:29]
    reg ex_reg_rs_lsb_1 : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_rs_lsb_1) @[Rocket.scala 248:26]
    skip
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    node _GEN_5 = mux(eq(UInt<2>("h1"), ex_reg_rs_lsb_1), mem_reg_wdata, UInt<64>("h0")) @[Rocket.scala 251:{14,14}]
    node _GEN_6 = mux(eq(UInt<2>("h2"), ex_reg_rs_lsb_1), wb_reg_wdata, _GEN_5) @[Rocket.scala 251:{14,14}]
    node _GEN_7 = mux(eq(UInt<2>("h3"), ex_reg_rs_lsb_1), io_dmem_resp_bits_data_word_bypass, _GEN_6) @[Rocket.scala 251:{14,14}]
    skip
    reg ex_reg_rs_msb_1 : UInt<62>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_rs_msb_1) @[Rocket.scala 249:26]
    node _T_3607 = cat(ex_reg_rs_msb_1, ex_reg_rs_lsb_1) @[Cat.scala 30:58]
    node ex_rs_1 = mux(ex_reg_rs_bypass_1, _GEN_7, _T_3607) @[Rocket.scala 251:14]
    node _T_3701 = asSInt(ex_rs_1) @[Rocket.scala 257:24]
    node _T_3709 = eq(UInt<2>("h3"), ex_ctrl_sel_alu2) @[Mux.scala 46:19]
    reg ex_ctrl_sel_imm : UInt<3>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_sel_imm) @[Rocket.scala 115:20]
    node _T_3609 = eq(ex_ctrl_sel_imm, UInt<3>("h5")) @[Rocket.scala 704:24]
    node _T_3611 = bits(ex_reg_inst, 31, 31) @[Rocket.scala 704:48]
    node _T_3612 = asSInt(_T_3611) @[Rocket.scala 704:53]
    node _T_3613 = mux(_T_3609, SInt<1>("h0"), _T_3612) @[Rocket.scala 704:19]
    node _T_3687 = asUInt(_T_3613) @[Cat.scala 30:58]
    node _T_3615 = eq(ex_ctrl_sel_imm, UInt<3>("h2")) @[Rocket.scala 705:26]
    node _T_3616 = bits(ex_reg_inst, 30, 20) @[Rocket.scala 705:41]
    node _T_3617 = asSInt(_T_3616) @[Rocket.scala 705:49]
    node _T_3618 = mux(_T_3615, _T_3617, pad(_T_3613, 11)) @[Rocket.scala 705:21]
    node _T_3686 = asUInt(_T_3618) @[Cat.scala 30:58]
    node _T_3688 = cat(_T_3687, _T_3686) @[Cat.scala 30:58]
    node _T_3620 = neq(ex_ctrl_sel_imm, UInt<3>("h2")) @[Rocket.scala 706:26]
    node _T_3622 = neq(ex_ctrl_sel_imm, UInt<3>("h3")) @[Rocket.scala 706:43]
    node _T_3623 = and(_T_3620, _T_3622) @[Rocket.scala 706:36]
    node _T_3624 = bits(ex_reg_inst, 19, 12) @[Rocket.scala 706:65]
    node _T_3625 = asSInt(_T_3624) @[Rocket.scala 706:73]
    node _T_3626 = mux(_T_3623, pad(_T_3613, 8), _T_3625) @[Rocket.scala 706:21]
    node _T_3684 = asUInt(_T_3626) @[Cat.scala 30:58]
    skip
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    node _T_3631 = or(_T_3615, _T_3609) @[Rocket.scala 707:33]
    node _T_3634 = eq(ex_ctrl_sel_imm, UInt<3>("h3")) @[Rocket.scala 708:23]
    node _T_3635 = bits(ex_reg_inst, 20, 20) @[Rocket.scala 708:39]
    node _T_3636 = asSInt(_T_3635) @[Rocket.scala 708:44]
    node _T_3638 = eq(ex_ctrl_sel_imm, UInt<3>("h1")) @[Rocket.scala 709:23]
    node _T_3639 = bits(ex_reg_inst, 7, 7) @[Rocket.scala 709:39]
    node _T_3640 = asSInt(_T_3639) @[Rocket.scala 709:43]
    node _T_3641 = mux(_T_3638, _T_3640, _T_3613) @[Rocket.scala 709:18]
    node _T_3642 = mux(_T_3634, _T_3636, _T_3641) @[Rocket.scala 708:18]
    node _T_3643 = mux(_T_3631, SInt<1>("h0"), _T_3642) @[Rocket.scala 707:18]
    node _T_3683 = asUInt(_T_3643) @[Cat.scala 30:58]
    node _T_3685 = cat(_T_3684, _T_3683) @[Cat.scala 30:58]
    node _T_3689 = cat(_T_3688, _T_3685) @[Cat.scala 30:58]
    skip
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    node _T_3650 = bits(ex_reg_inst, 30, 25) @[Rocket.scala 710:66]
    node _T_3651 = mux(_T_3631, UInt<6>("h0"), _T_3650) @[Rocket.scala 710:20]
    skip
    node _T_3656 = eq(ex_ctrl_sel_imm, UInt<3>("h0")) @[Rocket.scala 712:24]
    skip
    node _T_3659 = or(_T_3656, _T_3638) @[Rocket.scala 712:34]
    node _T_3660 = bits(ex_reg_inst, 11, 8) @[Rocket.scala 712:57]
    skip
    node _T_3663 = bits(ex_reg_inst, 19, 16) @[Rocket.scala 713:39]
    node _T_3664 = bits(ex_reg_inst, 24, 21) @[Rocket.scala 713:52]
    node _T_3665 = mux(_T_3609, _T_3663, _T_3664) @[Rocket.scala 713:19]
    node _T_3666 = mux(_T_3659, _T_3660, _T_3665) @[Rocket.scala 712:19]
    node _T_3667 = mux(_T_3615, UInt<4>("h0"), _T_3666) @[Rocket.scala 711:19]
    node _T_3681 = cat(_T_3651, _T_3667) @[Cat.scala 30:58]
    skip
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    node _T_3672 = eq(ex_ctrl_sel_imm, UInt<3>("h4")) @[Rocket.scala 715:22]
    skip
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    node _T_3676 = bits(ex_reg_inst, 15, 15) @[Rocket.scala 716:37]
    node _T_3678 = and(_T_3609, _T_3676) @[Rocket.scala 716:17]
    node _T_3679 = mux(_T_3672, _T_3635, _T_3678) @[Rocket.scala 715:17]
    node _T_3680 = mux(_T_3656, _T_3639, _T_3679) @[Rocket.scala 714:17]
    node _T_3682 = cat(_T_3681, _T_3680) @[Cat.scala 30:58]
    node _T_3690 = cat(_T_3689, _T_3682) @[Cat.scala 30:58]
    node ex_imm = asSInt(_T_3690) @[Rocket.scala 718:53]
    node _T_3707 = eq(UInt<2>("h1"), ex_ctrl_sel_alu2) @[Mux.scala 46:19]
    reg ex_reg_rvc : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_rvc) @[Rocket.scala 121:35]
    node _T_3706 = mux(ex_reg_rvc, SInt<4>("h2"), SInt<4>("h4")) @[Rocket.scala 259:19]
    node _T_3708 = mux(_T_3707, _T_3706, SInt<4>("h0")) @[Mux.scala 46:16]
    node _T_3710 = mux(_T_3709, ex_imm, pad(_T_3708, 32)) @[Mux.scala 46:16]
    node ex_op2 = mux(_T_3711, _T_3701, pad(_T_3710, 64)) @[Mux.scala 46:16]
    node alu_io_in2 = asUInt(ex_op2) @[Rocket.scala 264:24]
    skip
    node alu__T_17 = not(alu_io_in2) @[ALU.scala 61:35]
    node alu_in2_inv = mux(alu__T_16, alu__T_17, alu_io_in2) @[ALU.scala 61:20]
    reg ex_ctrl_sel_alu1 : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_sel_alu1) @[Rocket.scala 115:20]
    node _T_3698 = eq(UInt<2>("h1"), ex_ctrl_sel_alu1) @[Mux.scala 46:19]
    reg ex_reg_rs_bypass_0 : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_rs_bypass_0) @[Rocket.scala 247:29]
    reg ex_reg_rs_lsb_0 : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_rs_lsb_0) @[Rocket.scala 248:26]
    skip
    node _GEN_1 = mux(eq(UInt<2>("h1"), ex_reg_rs_lsb_0), mem_reg_wdata, UInt<64>("h0")) @[Rocket.scala 251:{14,14}]
    node _GEN_2 = mux(eq(UInt<2>("h2"), ex_reg_rs_lsb_0), wb_reg_wdata, _GEN_1) @[Rocket.scala 251:{14,14}]
    node _GEN_3 = mux(eq(UInt<2>("h3"), ex_reg_rs_lsb_0), io_dmem_resp_bits_data_word_bypass, _GEN_2) @[Rocket.scala 251:{14,14}]
    skip
    reg ex_reg_rs_msb_0 : UInt<62>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_rs_msb_0) @[Rocket.scala 249:26]
    node _T_3605 = cat(ex_reg_rs_msb_0, ex_reg_rs_lsb_0) @[Cat.scala 30:58]
    node ex_rs_0 = mux(ex_reg_rs_bypass_0, _GEN_3, _T_3605) @[Rocket.scala 251:14]
    node _T_3693 = asSInt(ex_rs_0) @[Rocket.scala 254:24]
    node _T_3696 = eq(UInt<2>("h2"), ex_ctrl_sel_alu1) @[Mux.scala 46:19]
    node _T_3695 = asSInt(ex_reg_pc) @[Rocket.scala 255:24]
    node _T_3697 = mux(_T_3696, _T_3695, SInt<40>("h0")) @[Mux.scala 46:16]
    node ex_op1 = mux(_T_3698, _T_3693, pad(_T_3697, 64)) @[Mux.scala 46:16]
    node alu_io_in1 = asUInt(ex_op1) @[Rocket.scala 265:24]
    skip
    node alu_in1_xor_in2 = xor(alu_io_in1, alu_in2_inv) @[ALU.scala 62:28]
    node alu__T_18 = add(alu_io_in1, alu_in2_inv) @[ALU.scala 63:26]
    node alu__T_19 = tail(alu__T_18, 1) @[ALU.scala 63:26]
    skip
    node _GEN_227 = pad(alu__T_16, 64) @[ALU.scala 63:36]
    node alu__T_21 = add(alu__T_19, _GEN_227) @[ALU.scala 63:36]
    node alu__T_22 = tail(alu__T_21, 1) @[ALU.scala 63:36]
    node alu__T_23 = bits(ex_ctrl_alu_fn, 0, 0) @[ALU.scala 44:35]
    skip
    node alu__T_26 = not(alu__T_16) @[ALU.scala 45:26]
    node alu__T_28 = eq(alu_in1_xor_in2, UInt<64>("h0")) @[ALU.scala 67:35]
    node alu__T_29 = bits(alu_io_in1, 63, 63) @[ALU.scala 68:15]
    node alu__T_30 = bits(alu_io_in2, 63, 63) @[ALU.scala 68:34]
    node alu__T_31 = eq(alu__T_29, alu__T_30) @[ALU.scala 68:24]
    skip
    node alu__T_32 = bits(alu__T_22, 63, 63) @[ALU.scala 68:56]
    node alu__T_33 = bits(ex_ctrl_alu_fn, 1, 1) @[ALU.scala 43:35]
    skip
    skip
    node alu__T_36 = mux(alu__T_33, alu__T_30, alu__T_29) @[ALU.scala 69:8]
    node alu__T_37 = mux(alu__T_31, alu__T_32, alu__T_36) @[ALU.scala 68:8]
    node alu__T_38 = mux(alu__T_26, alu__T_28, alu__T_37) @[ALU.scala 67:8]
    node alu__T_39 = xor(alu__T_23, alu__T_38) @[ALU.scala 66:36]
    skip
    node alu__T_41 = bits(alu_io_in1, 31, 31) @[ALU.scala 76:55]
    node alu__T_42 = and(alu__T_16, alu__T_41) @[ALU.scala 76:46]
    skip
    node alu__T_46 = mux(alu__T_42, UInt<32>("hffffffff"), UInt<32>("h0")) @[Bitwise.scala 71:12]
    reg ex_ctrl_alu_dw : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_alu_dw) @[Rocket.scala 115:20]
    skip
    skip
    node alu__T_49 = bits(alu_io_in1, 63, 32) @[ALU.scala 77:48]
    node alu__T_50 = mux(ex_ctrl_alu_dw, alu__T_49, alu__T_46) @[ALU.scala 77:24]
    node alu__T_51 = bits(alu_io_in2, 5, 5) @[ALU.scala 78:29]
    skip
    node alu__T_54 = and(alu__T_51, ex_ctrl_alu_dw) @[ALU.scala 78:33]
    node alu__T_55 = bits(alu_io_in2, 4, 0) @[ALU.scala 78:60]
    node alu_shamt = cat(alu__T_54, alu__T_55) @[Cat.scala 30:58]
    node alu__T_56 = bits(alu_io_in1, 31, 0) @[ALU.scala 79:34]
    node alu_shin_r = cat(alu__T_50, alu__T_56) @[Cat.scala 30:58]
    node alu__T_58 = eq(ex_ctrl_alu_fn, UInt<4>("h5")) @[ALU.scala 81:24]
    node alu__T_60 = eq(ex_ctrl_alu_fn, UInt<4>("hb")) @[ALU.scala 81:44]
    node alu__T_61 = or(alu__T_58, alu__T_60) @[ALU.scala 81:35]
    skip
    skip
    node alu__T_66 = shr(alu_shin_r, 32) @[Bitwise.scala 102:21]
    node _GEN_228 = pad(alu__T_66, 64) @[Bitwise.scala 102:31]
    node alu__T_67 = and(_GEN_228, UInt<64>("hffffffff")) @[Bitwise.scala 102:31]
    node alu__T_68 = bits(alu_shin_r, 31, 0) @[Bitwise.scala 102:46]
    node alu__T_69 = shl(alu__T_68, 32) @[Bitwise.scala 102:65]
    skip
    node alu__T_71 = and(alu__T_69, UInt<64>("hffffffff00000000")) @[Bitwise.scala 102:75]
    node alu__T_72 = or(alu__T_67, alu__T_71) @[Bitwise.scala 102:39]
    skip
    skip
    skip
    node alu__T_76 = shr(alu__T_72, 16) @[Bitwise.scala 102:21]
    node _GEN_229 = pad(alu__T_76, 64) @[Bitwise.scala 102:31]
    node alu__T_77 = and(_GEN_229, UInt<64>("hffff0000ffff")) @[Bitwise.scala 102:31]
    node alu__T_78 = bits(alu__T_72, 47, 0) @[Bitwise.scala 102:46]
    node alu__T_79 = shl(alu__T_78, 16) @[Bitwise.scala 102:65]
    skip
    node alu__T_81 = and(alu__T_79, UInt<64>("hffff0000ffff0000")) @[Bitwise.scala 102:75]
    node alu__T_82 = or(alu__T_77, alu__T_81) @[Bitwise.scala 102:39]
    skip
    skip
    skip
    node alu__T_86 = shr(alu__T_82, 8) @[Bitwise.scala 102:21]
    node _GEN_230 = pad(alu__T_86, 64) @[Bitwise.scala 102:31]
    node alu__T_87 = and(_GEN_230, UInt<64>("hff00ff00ff00ff")) @[Bitwise.scala 102:31]
    node alu__T_88 = bits(alu__T_82, 55, 0) @[Bitwise.scala 102:46]
    node alu__T_89 = shl(alu__T_88, 8) @[Bitwise.scala 102:65]
    skip
    node alu__T_91 = and(alu__T_89, UInt<64>("hff00ff00ff00ff00")) @[Bitwise.scala 102:75]
    node alu__T_92 = or(alu__T_87, alu__T_91) @[Bitwise.scala 102:39]
    skip
    skip
    skip
    node alu__T_96 = shr(alu__T_92, 4) @[Bitwise.scala 102:21]
    node _GEN_231 = pad(alu__T_96, 64) @[Bitwise.scala 102:31]
    node alu__T_97 = and(_GEN_231, UInt<64>("hf0f0f0f0f0f0f0f")) @[Bitwise.scala 102:31]
    node alu__T_98 = bits(alu__T_92, 59, 0) @[Bitwise.scala 102:46]
    node alu__T_99 = shl(alu__T_98, 4) @[Bitwise.scala 102:65]
    skip
    node alu__T_101 = and(alu__T_99, UInt<64>("hf0f0f0f0f0f0f0f0")) @[Bitwise.scala 102:75]
    node alu__T_102 = or(alu__T_97, alu__T_101) @[Bitwise.scala 102:39]
    skip
    skip
    skip
    node alu__T_106 = shr(alu__T_102, 2) @[Bitwise.scala 102:21]
    node _GEN_232 = pad(alu__T_106, 64) @[Bitwise.scala 102:31]
    node alu__T_107 = and(_GEN_232, UInt<64>("h3333333333333333")) @[Bitwise.scala 102:31]
    node alu__T_108 = bits(alu__T_102, 61, 0) @[Bitwise.scala 102:46]
    node alu__T_109 = shl(alu__T_108, 2) @[Bitwise.scala 102:65]
    skip
    node alu__T_111 = and(alu__T_109, UInt<64>("hcccccccccccccccc")) @[Bitwise.scala 102:75]
    node alu__T_112 = or(alu__T_107, alu__T_111) @[Bitwise.scala 102:39]
    skip
    skip
    skip
    node alu__T_116 = shr(alu__T_112, 1) @[Bitwise.scala 102:21]
    node _GEN_233 = pad(alu__T_116, 64) @[Bitwise.scala 102:31]
    node alu__T_117 = and(_GEN_233, UInt<64>("h5555555555555555")) @[Bitwise.scala 102:31]
    node alu__T_118 = bits(alu__T_112, 62, 0) @[Bitwise.scala 102:46]
    node alu__T_119 = shl(alu__T_118, 1) @[Bitwise.scala 102:65]
    skip
    node alu__T_121 = and(alu__T_119, UInt<64>("haaaaaaaaaaaaaaaa")) @[Bitwise.scala 102:75]
    node alu__T_122 = or(alu__T_117, alu__T_121) @[Bitwise.scala 102:39]
    node alu_shin = mux(alu__T_61, alu_shin_r, alu__T_122) @[ALU.scala 81:17]
    skip
    node alu__T_124 = bits(alu_shin, 63, 63) @[ALU.scala 82:41]
    node alu__T_125 = and(alu__T_16, alu__T_124) @[ALU.scala 82:35]
    node alu__T_126 = cat(alu__T_125, alu_shin) @[Cat.scala 30:58]
    node alu__T_127 = asSInt(alu__T_126) @[ALU.scala 82:57]
    node alu__T_128 = dshr(alu__T_127, alu_shamt) @[ALU.scala 82:64]
    node alu_shout_r = bits(alu__T_128, 63, 0) @[ALU.scala 82:73]
    skip
    skip
    node alu__T_133 = shr(alu_shout_r, 32) @[Bitwise.scala 102:21]
    node _GEN_234 = pad(alu__T_133, 64) @[Bitwise.scala 102:31]
    node alu__T_134 = and(_GEN_234, UInt<64>("hffffffff")) @[Bitwise.scala 102:31]
    node alu__T_135 = bits(alu_shout_r, 31, 0) @[Bitwise.scala 102:46]
    node alu__T_136 = shl(alu__T_135, 32) @[Bitwise.scala 102:65]
    skip
    node alu__T_138 = and(alu__T_136, UInt<64>("hffffffff00000000")) @[Bitwise.scala 102:75]
    node alu__T_139 = or(alu__T_134, alu__T_138) @[Bitwise.scala 102:39]
    skip
    skip
    skip
    node alu__T_143 = shr(alu__T_139, 16) @[Bitwise.scala 102:21]
    node _GEN_235 = pad(alu__T_143, 64) @[Bitwise.scala 102:31]
    node alu__T_144 = and(_GEN_235, UInt<64>("hffff0000ffff")) @[Bitwise.scala 102:31]
    node alu__T_145 = bits(alu__T_139, 47, 0) @[Bitwise.scala 102:46]
    node alu__T_146 = shl(alu__T_145, 16) @[Bitwise.scala 102:65]
    skip
    node alu__T_148 = and(alu__T_146, UInt<64>("hffff0000ffff0000")) @[Bitwise.scala 102:75]
    node alu__T_149 = or(alu__T_144, alu__T_148) @[Bitwise.scala 102:39]
    skip
    skip
    skip
    node alu__T_153 = shr(alu__T_149, 8) @[Bitwise.scala 102:21]
    node _GEN_236 = pad(alu__T_153, 64) @[Bitwise.scala 102:31]
    node alu__T_154 = and(_GEN_236, UInt<64>("hff00ff00ff00ff")) @[Bitwise.scala 102:31]
    node alu__T_155 = bits(alu__T_149, 55, 0) @[Bitwise.scala 102:46]
    node alu__T_156 = shl(alu__T_155, 8) @[Bitwise.scala 102:65]
    skip
    node alu__T_158 = and(alu__T_156, UInt<64>("hff00ff00ff00ff00")) @[Bitwise.scala 102:75]
    node alu__T_159 = or(alu__T_154, alu__T_158) @[Bitwise.scala 102:39]
    skip
    skip
    skip
    node alu__T_163 = shr(alu__T_159, 4) @[Bitwise.scala 102:21]
    node _GEN_237 = pad(alu__T_163, 64) @[Bitwise.scala 102:31]
    node alu__T_164 = and(_GEN_237, UInt<64>("hf0f0f0f0f0f0f0f")) @[Bitwise.scala 102:31]
    node alu__T_165 = bits(alu__T_159, 59, 0) @[Bitwise.scala 102:46]
    node alu__T_166 = shl(alu__T_165, 4) @[Bitwise.scala 102:65]
    skip
    node alu__T_168 = and(alu__T_166, UInt<64>("hf0f0f0f0f0f0f0f0")) @[Bitwise.scala 102:75]
    node alu__T_169 = or(alu__T_164, alu__T_168) @[Bitwise.scala 102:39]
    skip
    skip
    skip
    node alu__T_173 = shr(alu__T_169, 2) @[Bitwise.scala 102:21]
    node _GEN_238 = pad(alu__T_173, 64) @[Bitwise.scala 102:31]
    node alu__T_174 = and(_GEN_238, UInt<64>("h3333333333333333")) @[Bitwise.scala 102:31]
    node alu__T_175 = bits(alu__T_169, 61, 0) @[Bitwise.scala 102:46]
    node alu__T_176 = shl(alu__T_175, 2) @[Bitwise.scala 102:65]
    skip
    node alu__T_178 = and(alu__T_176, UInt<64>("hcccccccccccccccc")) @[Bitwise.scala 102:75]
    node alu__T_179 = or(alu__T_174, alu__T_178) @[Bitwise.scala 102:39]
    skip
    skip
    skip
    node alu__T_183 = shr(alu__T_179, 1) @[Bitwise.scala 102:21]
    node _GEN_239 = pad(alu__T_183, 64) @[Bitwise.scala 102:31]
    node alu__T_184 = and(_GEN_239, UInt<64>("h5555555555555555")) @[Bitwise.scala 102:31]
    node alu__T_185 = bits(alu__T_179, 62, 0) @[Bitwise.scala 102:46]
    node alu__T_186 = shl(alu__T_185, 1) @[Bitwise.scala 102:65]
    skip
    node alu__T_188 = and(alu__T_186, UInt<64>("haaaaaaaaaaaaaaaa")) @[Bitwise.scala 102:75]
    node alu_shout_l = or(alu__T_184, alu__T_188) @[Bitwise.scala 102:39]
    skip
    skip
    skip
    node alu__T_195 = mux(alu__T_61, alu_shout_r, UInt<64>("h0")) @[ALU.scala 84:18]
    node alu__T_197 = eq(ex_ctrl_alu_fn, UInt<4>("h1")) @[ALU.scala 85:25]
    node alu__T_199 = mux(alu__T_197, alu_shout_l, UInt<64>("h0")) @[ALU.scala 85:18]
    node alu_shout = or(alu__T_195, alu__T_199) @[ALU.scala 84:74]
    node alu__T_201 = eq(ex_ctrl_alu_fn, UInt<4>("h4")) @[ALU.scala 88:25]
    node alu__T_203 = eq(ex_ctrl_alu_fn, UInt<4>("h6")) @[ALU.scala 88:45]
    node alu__T_204 = or(alu__T_201, alu__T_203) @[ALU.scala 88:36]
    node alu__T_206 = mux(alu__T_204, alu_in1_xor_in2, UInt<64>("h0")) @[ALU.scala 88:18]
    skip
    node alu__T_210 = eq(ex_ctrl_alu_fn, UInt<4>("h7")) @[ALU.scala 89:44]
    node alu__T_211 = or(alu__T_203, alu__T_210) @[ALU.scala 89:35]
    node alu__T_212 = and(alu_io_in1, alu_io_in2) @[ALU.scala 89:63]
    node alu__T_214 = mux(alu__T_211, alu__T_212, UInt<64>("h0")) @[ALU.scala 89:18]
    node alu_logic = or(alu__T_206, alu__T_214) @[ALU.scala 88:78]
    node alu__T_216 = eq(ex_ctrl_alu_fn, UInt<4>("h2")) @[ALU.scala 42:30]
    node alu__T_218 = eq(ex_ctrl_alu_fn, UInt<4>("h3")) @[ALU.scala 42:48]
    node alu__T_219 = or(alu__T_216, alu__T_218) @[ALU.scala 42:41]
    node alu__T_221 = geq(ex_ctrl_alu_fn, UInt<4>("hc")) @[ALU.scala 42:66]
    node alu__T_222 = or(alu__T_219, alu__T_221) @[ALU.scala 42:59]
    skip
    node alu__T_223 = and(alu__T_222, alu__T_39) @[ALU.scala 90:35]
    node _GEN_240 = pad(alu__T_223, 64) @[ALU.scala 90:50]
    node alu__T_224 = or(_GEN_240, alu_logic) @[ALU.scala 90:50]
    node alu_shift_logic = or(alu__T_224, alu_shout) @[ALU.scala 90:58]
    node alu__T_226 = eq(ex_ctrl_alu_fn, UInt<4>("h0")) @[ALU.scala 91:23]
    node alu__T_228 = eq(ex_ctrl_alu_fn, UInt<4>("ha")) @[ALU.scala 91:43]
    node alu__T_229 = or(alu__T_226, alu__T_228) @[ALU.scala 91:34]
    node alu_out = mux(alu__T_229, alu__T_22, alu_shift_logic) @[ALU.scala 91:16]
    node alu__T_231 = not(ex_ctrl_alu_dw) @[ALU.scala 96:17]
    node alu__T_232 = bits(alu_out, 31, 31) @[ALU.scala 96:56]
    skip
    node alu__T_236 = mux(alu__T_232, UInt<32>("hffffffff"), UInt<32>("h0")) @[Bitwise.scala 71:12]
    node alu__T_237 = bits(alu_out, 31, 0) @[ALU.scala 96:66]
    node alu__T_238 = cat(alu__T_236, alu__T_237) @[Cat.scala 30:58]
    node alu__GEN_0 = mux(alu__T_231, alu__T_238, alu_out) @[ALU.scala 93:10 96:{28,37}]
    skip
    reg div_req_dw : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), div_req_dw) @[Multiplier.scala 47:16]
    skip
    skip
    reg div_req_tag : UInt<5>, const_clock with :
      reset => (UInt<1>("h0"), div_req_tag) @[Multiplier.scala 47:16]
    reg div_count : UInt<7>, const_clock with :
      reset => (UInt<1>("h0"), div_count) @[Multiplier.scala 48:18]
    reg div_neg_out : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), div_neg_out) @[Multiplier.scala 49:20]
    reg div_isMul : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), div_isMul) @[Multiplier.scala 50:18]
    reg div_isHi : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), div_isHi) @[Multiplier.scala 51:17]
    reg div_divisor : UInt<65>, const_clock with :
      reset => (UInt<1>("h0"), div_divisor) @[Multiplier.scala 52:20]
    reg div_remainder : UInt<130>, const_clock with :
      reset => (UInt<1>("h0"), div_remainder) @[Multiplier.scala 53:22]
    skip
    node div__T_79 = and(ex_ctrl_alu_fn, UInt<4>("h4")) @[Decode.scala 13:65]
    node div__T_81 = eq(div__T_79, UInt<4>("h0")) @[Decode.scala 13:121]
    node div__T_83 = and(ex_ctrl_alu_fn, UInt<4>("h8")) @[Decode.scala 13:65]
    node div__T_85 = eq(div__T_83, UInt<4>("h8")) @[Decode.scala 13:121]
    skip
    node div__T_88 = or(div__T_81, div__T_85) @[Decode.scala 14:30]
    node div__T_90 = and(ex_ctrl_alu_fn, UInt<4>("h5")) @[Decode.scala 13:65]
    node div__T_92 = eq(div__T_90, UInt<4>("h1")) @[Decode.scala 13:121]
    node div__T_94 = and(ex_ctrl_alu_fn, UInt<4>("h2")) @[Decode.scala 13:65]
    node div__T_96 = eq(div__T_94, UInt<4>("h2")) @[Decode.scala 13:121]
    skip
    node div__T_99 = or(div__T_92, div__T_96) @[Decode.scala 14:30]
    node div__T_100 = or(div__T_99, div__T_85) @[Decode.scala 14:30]
    node div__T_102 = and(ex_ctrl_alu_fn, UInt<4>("h9")) @[Decode.scala 13:65]
    node div__T_104 = eq(div__T_102, UInt<4>("h0")) @[Decode.scala 13:121]
    node div__T_106 = and(ex_ctrl_alu_fn, UInt<4>("h3")) @[Decode.scala 13:65]
    node div__T_108 = eq(div__T_106, UInt<4>("h0")) @[Decode.scala 13:121]
    skip
    node div__T_111 = or(div__T_104, div__T_81) @[Decode.scala 14:30]
    node div__T_112 = or(div__T_111, div__T_108) @[Decode.scala 14:30]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    node div__T_120 = bits(ex_rs_0, 31, 31) @[Multiplier.scala 70:38]
    node div__T_121 = bits(ex_rs_0, 63, 63) @[Multiplier.scala 70:48]
    node div__T_122 = mux(alu__T_231, div__T_120, div__T_121) @[Multiplier.scala 70:29]
    node div_lhs_sign = and(div__T_112, div__T_122) @[Multiplier.scala 70:23]
    skip
    node div__T_126 = mux(div_lhs_sign, UInt<32>("hffffffff"), UInt<32>("h0")) @[Bitwise.scala 71:12]
    node div__T_127 = bits(ex_rs_0, 63, 32) @[Multiplier.scala 71:43]
    node div__T_128 = mux(alu__T_231, div__T_126, div__T_127) @[Multiplier.scala 71:17]
    node div__T_129 = bits(ex_rs_0, 31, 0) @[Multiplier.scala 72:15]
    node div_lhs_in = cat(div__T_128, div__T_129) @[Cat.scala 30:58]
    skip
    skip
    skip
    node div__T_134 = bits(ex_rs_1, 31, 31) @[Multiplier.scala 70:38]
    node div__T_135 = bits(ex_rs_1, 63, 63) @[Multiplier.scala 70:48]
    node div__T_136 = mux(alu__T_231, div__T_134, div__T_135) @[Multiplier.scala 70:29]
    node div_rhs_sign = and(div__T_111, div__T_136) @[Multiplier.scala 70:23]
    skip
    node div__T_140 = mux(div_rhs_sign, UInt<32>("hffffffff"), UInt<32>("h0")) @[Bitwise.scala 71:12]
    node div__T_141 = bits(ex_rs_1, 63, 32) @[Multiplier.scala 71:43]
    node div__T_142 = mux(alu__T_231, div__T_140, div__T_141) @[Multiplier.scala 71:17]
    node div__T_143 = bits(ex_rs_1, 31, 0) @[Multiplier.scala 72:15]
    node div_rhs_in = cat(div__T_142, div__T_143) @[Cat.scala 30:58]
    node div__T_144 = bits(div_remainder, 128, 64) @[Multiplier.scala 77:29]
    node div__T_145 = sub(div__T_144, div_divisor) @[Multiplier.scala 77:37]
    skip
    node div_subtractor = tail(div__T_145, 1) @[Multiplier.scala 77:37]
    node div__T_147 = bits(div_remainder, 63, 0) @[Multiplier.scala 78:37]
    node div__T_149 = sub(UInt<64>("h0"), div__T_147) @[Multiplier.scala 78:27]
    skip
    node div_negated_remainder = tail(div__T_149, 1) @[Multiplier.scala 78:27]
    node div__T_151 = eq(div_state, UInt<3>("h1")) @[Multiplier.scala 80:15]
    node div__T_152 = bits(div_remainder, 63, 63) @[Multiplier.scala 81:20]
    node div__T_153 = or(div__T_152, div_isMul) @[Multiplier.scala 81:26]
    node div__GEN_0 = mux(div__T_153, pad(div_negated_remainder, 130), div_remainder) @[Multiplier.scala 81:36 82:17 53:22]
    node div__T_154 = bits(div_divisor, 63, 63) @[Multiplier.scala 84:18]
    node div__T_155 = or(div__T_154, div_isMul) @[Multiplier.scala 84:24]
    node div__GEN_1 = mux(div__T_155, div_subtractor, div_divisor) @[Multiplier.scala 84:34 85:15 52:20]
    node div__GEN_2 = mux(div__T_151, div__GEN_0, div_remainder) @[Multiplier.scala 53:22 80:33]
    node div__GEN_3 = mux(div__T_151, div__GEN_1, div_divisor) @[Multiplier.scala 52:20 80:33]
    node div__GEN_4 = mux(div__T_151, UInt<3>("h2"), div_state) @[Multiplier.scala 80:33 87:11 45:18]
    node div__T_156 = eq(div_state, UInt<3>("h4")) @[Multiplier.scala 90:15]
    node div__GEN_5 = mux(div__T_156, pad(div_negated_remainder, 130), div__GEN_2) @[Multiplier.scala 90:33 91:15]
    node div__GEN_6 = mux(div__T_156, UInt<3>("h5"), div__GEN_4) @[Multiplier.scala 90:33 92:11]
    node div__T_157 = eq(div_state, UInt<3>("h3")) @[Multiplier.scala 94:15]
    node div__T_158 = bits(div_remainder, 128, 65) @[Multiplier.scala 95:27]
    node div__T_159 = mux(div_neg_out, UInt<3>("h4"), UInt<3>("h5")) @[Multiplier.scala 96:17]
    node div__GEN_7 = mux(div__T_157, pad(div__T_158, 130), div__GEN_5) @[Multiplier.scala 94:31 95:15]
    node div__GEN_8 = mux(div__T_157, div__T_159, div__GEN_6) @[Multiplier.scala 94:31 96:11]
    node div__T_160 = eq(div_state, UInt<3>("h2")) @[Multiplier.scala 98:15]
    node div__T_161 = and(div__T_160, div_isMul) @[Multiplier.scala 98:26]
    node div__T_162 = bits(div_remainder, 129, 65) @[Multiplier.scala 99:31]
    skip
    node div__T_164 = cat(div__T_162, div__T_147) @[Cat.scala 30:58]
    node div__T_165 = bits(div__T_164, 63, 0) @[Multiplier.scala 100:24]
    node div__T_166 = bits(div__T_164, 128, 64) @[Multiplier.scala 101:23]
    node div__T_167 = asSInt(div__T_166) @[Multiplier.scala 101:37]
    node div__T_168 = asSInt(div_divisor) @[Multiplier.scala 102:26]
    node div__T_169 = bits(div__T_165, 7, 0) @[Multiplier.scala 103:22]
    node div__M_170 = asSInt(div__T_169) @[Multiplier.scala 103:22]
    node div__T_170 = mul(div__T_168, div__M_170) @[Multiplier.scala 103:43]
    node _GEN_241 = pad(div__T_167, 73) @[Multiplier.scala 103:52]
    node div__T_171 = add(div__T_170, _GEN_241) @[Multiplier.scala 103:52]
    node div__T_172 = tail(div__T_171, 1) @[Multiplier.scala 103:52]
    node div__T_173 = asSInt(div__T_172) @[Multiplier.scala 103:52]
    node div__T_174 = bits(div__T_165, 63, 8) @[Multiplier.scala 104:38]
    node div__T_175 = asUInt(div__T_173) @[Cat.scala 30:58]
    node div__T_176 = cat(div__T_175, div__T_174) @[Cat.scala 30:58]
    node div__T_179 = mul(div_count, UInt<4>("h8")) @[Multiplier.scala 106:56]
    node div__T_180 = bits(div__T_179, 5, 0) @[Multiplier.scala 106:72]
    node div__T_181 = dshr(SInt<65>("h-10000000000000000"), div__T_180) @[Multiplier.scala 106:46]
    node div__T_182 = bits(div__T_181, 63, 0) @[Multiplier.scala 106:91]
    node div__T_185 = neq(div_count, UInt<7>("h7")) @[Multiplier.scala 107:47]
    skip
    node div__T_188 = neq(div_count, UInt<7>("h0")) @[Multiplier.scala 107:81]
    node div__T_189 = and(div__T_185, div__T_188) @[Multiplier.scala 107:72]
    node div__T_191 = not(div_isHi) @[Multiplier.scala 108:7]
    node div__T_192 = and(div__T_189, div__T_191) @[Multiplier.scala 107:87]
    node div__T_193 = not(div__T_182) @[Multiplier.scala 108:26]
    node div__T_194 = and(div__T_165, div__T_193) @[Multiplier.scala 108:24]
    node div__T_196 = eq(div__T_194, UInt<64>("h0")) @[Multiplier.scala 108:37]
    node div__T_197 = and(div__T_192, div__T_196) @[Multiplier.scala 108:13]
    skip
    node div__T_201 = sub(UInt<11>("h40"), div__T_179) @[Multiplier.scala 109:36]
    skip
    node div__T_203 = tail(div__T_201, 1) @[Multiplier.scala 109:36]
    node div__T_204 = bits(div__T_203, 5, 0) @[Multiplier.scala 109:60]
    node div__T_205 = dshr(div__T_164, div__T_204) @[Multiplier.scala 109:27]
    node div__T_206 = bits(div__T_176, 128, 64) @[Multiplier.scala 110:37]
    node div__T_207 = mux(div__T_197, div__T_205, div__T_176) @[Multiplier.scala 110:55]
    node div__T_208 = bits(div__T_207, 63, 0) @[Multiplier.scala 110:82]
    node div__T_209 = cat(div__T_206, div__T_208) @[Cat.scala 30:58]
    node div__T_210 = shr(div__T_209, 64) @[Multiplier.scala 111:34]
    node div__T_212 = bits(div__T_209, 63, 0) @[Multiplier.scala 111:64]
    node div__T_213 = cat(div__T_210, UInt<1>("h0")) @[Cat.scala 30:58]
    node div__T_214 = cat(div__T_213, div__T_212) @[Cat.scala 30:58]
    node div__T_216 = add(div_count, UInt<7>("h1")) @[Multiplier.scala 113:20]
    node div__T_217 = tail(div__T_216, 1) @[Multiplier.scala 113:20]
    node div__T_219 = eq(div_count, UInt<7>("h7")) @[Multiplier.scala 114:25]
    node div__T_220 = or(div__T_197, div__T_219) @[Multiplier.scala 114:16]
    node div__T_221 = mux(div_isHi, UInt<3>("h3"), UInt<3>("h5")) @[Multiplier.scala 115:19]
    node div__GEN_9 = mux(div__T_220, div__T_221, div__GEN_8) @[Multiplier.scala 114:51 115:13]
    node div__GEN_10 = mux(div__T_161, div__T_214, div__GEN_7) @[Multiplier.scala 111:15 98:36]
    node div__GEN_11 = mux(div__T_161, div__T_217, div_count) @[Multiplier.scala 113:11 48:18 98:36]
    node div__GEN_12 = mux(div__T_161, div__GEN_9, div__GEN_8) @[Multiplier.scala 98:36]
    skip
    node div__T_224 = not(div_isMul) @[Multiplier.scala 118:29]
    node div__T_225 = and(div__T_160, div__T_224) @[Multiplier.scala 118:26]
    node div__T_226 = bits(div_subtractor, 64, 64) @[Multiplier.scala 122:28]
    node div__T_227 = bits(div_remainder, 127, 64) @[Multiplier.scala 123:24]
    node div__T_228 = bits(div_subtractor, 63, 0) @[Multiplier.scala 123:45]
    node div__T_229 = mux(div__T_226, div__T_227, div__T_228) @[Multiplier.scala 123:14]
    skip
    node div__T_232 = not(div__T_226) @[Multiplier.scala 123:67]
    node div__T_233 = cat(div__T_229, div__T_147) @[Cat.scala 30:58]
    node div__T_234 = cat(div__T_233, div__T_232) @[Cat.scala 30:58]
    node div__T_236 = eq(div_count, UInt<7>("h40")) @[Multiplier.scala 127:17]
    skip
    node div__T_238 = mux(div_isHi, UInt<3>("h3"), div__T_159) @[Multiplier.scala 128:19]
    node div__GEN_13 = mux(div__T_236, div__T_238, div__GEN_12) @[Multiplier.scala 127:38 128:13]
    skip
    skip
    node div__T_243 = eq(div_count, UInt<7>("h0")) @[Multiplier.scala 134:24]
    skip
    skip
    node div__T_247 = and(div__T_243, div__T_232) @[Multiplier.scala 134:30]
    node div__T_248 = bits(div_divisor, 63, 0) @[Multiplier.scala 136:36]
    node div__T_249 = bits(div__T_248, 63, 32) @[CircuitMath.scala 35:17]
    node div__T_250 = bits(div__T_248, 31, 0) @[CircuitMath.scala 36:17]
    node div__T_252 = neq(div__T_249, UInt<32>("h0")) @[CircuitMath.scala 37:22]
    node div__T_253 = bits(div__T_249, 31, 16) @[CircuitMath.scala 35:17]
    node div__T_254 = bits(div__T_249, 15, 0) @[CircuitMath.scala 36:17]
    node div__T_256 = neq(div__T_253, UInt<16>("h0")) @[CircuitMath.scala 37:22]
    node div__T_257 = bits(div__T_253, 15, 8) @[CircuitMath.scala 35:17]
    node div__T_258 = bits(div__T_253, 7, 0) @[CircuitMath.scala 36:17]
    node div__T_260 = neq(div__T_257, UInt<8>("h0")) @[CircuitMath.scala 37:22]
    node div__T_261 = bits(div__T_257, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_262 = bits(div__T_257, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_264 = neq(div__T_261, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_265 = bits(div__T_261, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_267 = bits(div__T_261, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_269 = bits(div__T_261, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_270 = mux(div__T_267, UInt<2>("h2"), pad(div__T_269, 2)) @[CircuitMath.scala 32:10]
    node div__T_271 = mux(div__T_265, UInt<2>("h3"), div__T_270) @[CircuitMath.scala 32:10]
    node div__T_272 = bits(div__T_262, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_274 = bits(div__T_262, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_276 = bits(div__T_262, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_277 = mux(div__T_274, UInt<2>("h2"), pad(div__T_276, 2)) @[CircuitMath.scala 32:10]
    node div__T_278 = mux(div__T_272, UInt<2>("h3"), div__T_277) @[CircuitMath.scala 32:10]
    node div__T_279 = mux(div__T_264, div__T_271, div__T_278) @[CircuitMath.scala 38:21]
    node div__T_280 = cat(div__T_264, div__T_279) @[Cat.scala 30:58]
    node div__T_281 = bits(div__T_258, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_282 = bits(div__T_258, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_284 = neq(div__T_281, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_285 = bits(div__T_281, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_287 = bits(div__T_281, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_289 = bits(div__T_281, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_290 = mux(div__T_287, UInt<2>("h2"), pad(div__T_289, 2)) @[CircuitMath.scala 32:10]
    node div__T_291 = mux(div__T_285, UInt<2>("h3"), div__T_290) @[CircuitMath.scala 32:10]
    node div__T_292 = bits(div__T_282, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_294 = bits(div__T_282, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_296 = bits(div__T_282, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_297 = mux(div__T_294, UInt<2>("h2"), pad(div__T_296, 2)) @[CircuitMath.scala 32:10]
    node div__T_298 = mux(div__T_292, UInt<2>("h3"), div__T_297) @[CircuitMath.scala 32:10]
    node div__T_299 = mux(div__T_284, div__T_291, div__T_298) @[CircuitMath.scala 38:21]
    node div__T_300 = cat(div__T_284, div__T_299) @[Cat.scala 30:58]
    node div__T_301 = mux(div__T_260, div__T_280, div__T_300) @[CircuitMath.scala 38:21]
    node div__T_302 = cat(div__T_260, div__T_301) @[Cat.scala 30:58]
    node div__T_303 = bits(div__T_254, 15, 8) @[CircuitMath.scala 35:17]
    node div__T_304 = bits(div__T_254, 7, 0) @[CircuitMath.scala 36:17]
    node div__T_306 = neq(div__T_303, UInt<8>("h0")) @[CircuitMath.scala 37:22]
    node div__T_307 = bits(div__T_303, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_308 = bits(div__T_303, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_310 = neq(div__T_307, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_311 = bits(div__T_307, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_313 = bits(div__T_307, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_315 = bits(div__T_307, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_316 = mux(div__T_313, UInt<2>("h2"), pad(div__T_315, 2)) @[CircuitMath.scala 32:10]
    node div__T_317 = mux(div__T_311, UInt<2>("h3"), div__T_316) @[CircuitMath.scala 32:10]
    node div__T_318 = bits(div__T_308, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_320 = bits(div__T_308, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_322 = bits(div__T_308, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_323 = mux(div__T_320, UInt<2>("h2"), pad(div__T_322, 2)) @[CircuitMath.scala 32:10]
    node div__T_324 = mux(div__T_318, UInt<2>("h3"), div__T_323) @[CircuitMath.scala 32:10]
    node div__T_325 = mux(div__T_310, div__T_317, div__T_324) @[CircuitMath.scala 38:21]
    node div__T_326 = cat(div__T_310, div__T_325) @[Cat.scala 30:58]
    node div__T_327 = bits(div__T_304, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_328 = bits(div__T_304, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_330 = neq(div__T_327, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_331 = bits(div__T_327, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_333 = bits(div__T_327, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_335 = bits(div__T_327, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_336 = mux(div__T_333, UInt<2>("h2"), pad(div__T_335, 2)) @[CircuitMath.scala 32:10]
    node div__T_337 = mux(div__T_331, UInt<2>("h3"), div__T_336) @[CircuitMath.scala 32:10]
    node div__T_338 = bits(div__T_328, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_340 = bits(div__T_328, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_342 = bits(div__T_328, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_343 = mux(div__T_340, UInt<2>("h2"), pad(div__T_342, 2)) @[CircuitMath.scala 32:10]
    node div__T_344 = mux(div__T_338, UInt<2>("h3"), div__T_343) @[CircuitMath.scala 32:10]
    node div__T_345 = mux(div__T_330, div__T_337, div__T_344) @[CircuitMath.scala 38:21]
    node div__T_346 = cat(div__T_330, div__T_345) @[Cat.scala 30:58]
    node div__T_347 = mux(div__T_306, div__T_326, div__T_346) @[CircuitMath.scala 38:21]
    node div__T_348 = cat(div__T_306, div__T_347) @[Cat.scala 30:58]
    node div__T_349 = mux(div__T_256, div__T_302, div__T_348) @[CircuitMath.scala 38:21]
    node div__T_350 = cat(div__T_256, div__T_349) @[Cat.scala 30:58]
    node div__T_351 = bits(div__T_250, 31, 16) @[CircuitMath.scala 35:17]
    node div__T_352 = bits(div__T_250, 15, 0) @[CircuitMath.scala 36:17]
    node div__T_354 = neq(div__T_351, UInt<16>("h0")) @[CircuitMath.scala 37:22]
    node div__T_355 = bits(div__T_351, 15, 8) @[CircuitMath.scala 35:17]
    node div__T_356 = bits(div__T_351, 7, 0) @[CircuitMath.scala 36:17]
    node div__T_358 = neq(div__T_355, UInt<8>("h0")) @[CircuitMath.scala 37:22]
    node div__T_359 = bits(div__T_355, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_360 = bits(div__T_355, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_362 = neq(div__T_359, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_363 = bits(div__T_359, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_365 = bits(div__T_359, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_367 = bits(div__T_359, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_368 = mux(div__T_365, UInt<2>("h2"), pad(div__T_367, 2)) @[CircuitMath.scala 32:10]
    node div__T_369 = mux(div__T_363, UInt<2>("h3"), div__T_368) @[CircuitMath.scala 32:10]
    node div__T_370 = bits(div__T_360, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_372 = bits(div__T_360, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_374 = bits(div__T_360, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_375 = mux(div__T_372, UInt<2>("h2"), pad(div__T_374, 2)) @[CircuitMath.scala 32:10]
    node div__T_376 = mux(div__T_370, UInt<2>("h3"), div__T_375) @[CircuitMath.scala 32:10]
    node div__T_377 = mux(div__T_362, div__T_369, div__T_376) @[CircuitMath.scala 38:21]
    node div__T_378 = cat(div__T_362, div__T_377) @[Cat.scala 30:58]
    node div__T_379 = bits(div__T_356, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_380 = bits(div__T_356, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_382 = neq(div__T_379, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_383 = bits(div__T_379, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_385 = bits(div__T_379, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_387 = bits(div__T_379, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_388 = mux(div__T_385, UInt<2>("h2"), pad(div__T_387, 2)) @[CircuitMath.scala 32:10]
    node div__T_389 = mux(div__T_383, UInt<2>("h3"), div__T_388) @[CircuitMath.scala 32:10]
    node div__T_390 = bits(div__T_380, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_392 = bits(div__T_380, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_394 = bits(div__T_380, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_395 = mux(div__T_392, UInt<2>("h2"), pad(div__T_394, 2)) @[CircuitMath.scala 32:10]
    node div__T_396 = mux(div__T_390, UInt<2>("h3"), div__T_395) @[CircuitMath.scala 32:10]
    node div__T_397 = mux(div__T_382, div__T_389, div__T_396) @[CircuitMath.scala 38:21]
    node div__T_398 = cat(div__T_382, div__T_397) @[Cat.scala 30:58]
    node div__T_399 = mux(div__T_358, div__T_378, div__T_398) @[CircuitMath.scala 38:21]
    node div__T_400 = cat(div__T_358, div__T_399) @[Cat.scala 30:58]
    node div__T_401 = bits(div__T_352, 15, 8) @[CircuitMath.scala 35:17]
    node div__T_402 = bits(div__T_352, 7, 0) @[CircuitMath.scala 36:17]
    node div__T_404 = neq(div__T_401, UInt<8>("h0")) @[CircuitMath.scala 37:22]
    node div__T_405 = bits(div__T_401, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_406 = bits(div__T_401, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_408 = neq(div__T_405, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_409 = bits(div__T_405, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_411 = bits(div__T_405, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_413 = bits(div__T_405, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_414 = mux(div__T_411, UInt<2>("h2"), pad(div__T_413, 2)) @[CircuitMath.scala 32:10]
    node div__T_415 = mux(div__T_409, UInt<2>("h3"), div__T_414) @[CircuitMath.scala 32:10]
    node div__T_416 = bits(div__T_406, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_418 = bits(div__T_406, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_420 = bits(div__T_406, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_421 = mux(div__T_418, UInt<2>("h2"), pad(div__T_420, 2)) @[CircuitMath.scala 32:10]
    node div__T_422 = mux(div__T_416, UInt<2>("h3"), div__T_421) @[CircuitMath.scala 32:10]
    node div__T_423 = mux(div__T_408, div__T_415, div__T_422) @[CircuitMath.scala 38:21]
    node div__T_424 = cat(div__T_408, div__T_423) @[Cat.scala 30:58]
    node div__T_425 = bits(div__T_402, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_426 = bits(div__T_402, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_428 = neq(div__T_425, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_429 = bits(div__T_425, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_431 = bits(div__T_425, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_433 = bits(div__T_425, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_434 = mux(div__T_431, UInt<2>("h2"), pad(div__T_433, 2)) @[CircuitMath.scala 32:10]
    node div__T_435 = mux(div__T_429, UInt<2>("h3"), div__T_434) @[CircuitMath.scala 32:10]
    node div__T_436 = bits(div__T_426, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_438 = bits(div__T_426, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_440 = bits(div__T_426, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_441 = mux(div__T_438, UInt<2>("h2"), pad(div__T_440, 2)) @[CircuitMath.scala 32:10]
    node div__T_442 = mux(div__T_436, UInt<2>("h3"), div__T_441) @[CircuitMath.scala 32:10]
    node div__T_443 = mux(div__T_428, div__T_435, div__T_442) @[CircuitMath.scala 38:21]
    node div__T_444 = cat(div__T_428, div__T_443) @[Cat.scala 30:58]
    node div__T_445 = mux(div__T_404, div__T_424, div__T_444) @[CircuitMath.scala 38:21]
    node div__T_446 = cat(div__T_404, div__T_445) @[Cat.scala 30:58]
    node div__T_447 = mux(div__T_354, div__T_400, div__T_446) @[CircuitMath.scala 38:21]
    node div__T_448 = cat(div__T_354, div__T_447) @[Cat.scala 30:58]
    node div__T_449 = mux(div__T_252, div__T_350, div__T_448) @[CircuitMath.scala 38:21]
    node div__T_450 = cat(div__T_252, div__T_449) @[Cat.scala 30:58]
    skip
    node div__T_452 = bits(div__T_147, 63, 32) @[CircuitMath.scala 35:17]
    node div__T_453 = bits(div__T_147, 31, 0) @[CircuitMath.scala 36:17]
    node div__T_455 = neq(div__T_452, UInt<32>("h0")) @[CircuitMath.scala 37:22]
    node div__T_456 = bits(div__T_452, 31, 16) @[CircuitMath.scala 35:17]
    node div__T_457 = bits(div__T_452, 15, 0) @[CircuitMath.scala 36:17]
    node div__T_459 = neq(div__T_456, UInt<16>("h0")) @[CircuitMath.scala 37:22]
    node div__T_460 = bits(div__T_456, 15, 8) @[CircuitMath.scala 35:17]
    node div__T_461 = bits(div__T_456, 7, 0) @[CircuitMath.scala 36:17]
    node div__T_463 = neq(div__T_460, UInt<8>("h0")) @[CircuitMath.scala 37:22]
    node div__T_464 = bits(div__T_460, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_465 = bits(div__T_460, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_467 = neq(div__T_464, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_468 = bits(div__T_464, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_470 = bits(div__T_464, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_472 = bits(div__T_464, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_473 = mux(div__T_470, UInt<2>("h2"), pad(div__T_472, 2)) @[CircuitMath.scala 32:10]
    node div__T_474 = mux(div__T_468, UInt<2>("h3"), div__T_473) @[CircuitMath.scala 32:10]
    node div__T_475 = bits(div__T_465, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_477 = bits(div__T_465, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_479 = bits(div__T_465, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_480 = mux(div__T_477, UInt<2>("h2"), pad(div__T_479, 2)) @[CircuitMath.scala 32:10]
    node div__T_481 = mux(div__T_475, UInt<2>("h3"), div__T_480) @[CircuitMath.scala 32:10]
    node div__T_482 = mux(div__T_467, div__T_474, div__T_481) @[CircuitMath.scala 38:21]
    node div__T_483 = cat(div__T_467, div__T_482) @[Cat.scala 30:58]
    node div__T_484 = bits(div__T_461, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_485 = bits(div__T_461, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_487 = neq(div__T_484, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_488 = bits(div__T_484, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_490 = bits(div__T_484, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_492 = bits(div__T_484, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_493 = mux(div__T_490, UInt<2>("h2"), pad(div__T_492, 2)) @[CircuitMath.scala 32:10]
    node div__T_494 = mux(div__T_488, UInt<2>("h3"), div__T_493) @[CircuitMath.scala 32:10]
    node div__T_495 = bits(div__T_485, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_497 = bits(div__T_485, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_499 = bits(div__T_485, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_500 = mux(div__T_497, UInt<2>("h2"), pad(div__T_499, 2)) @[CircuitMath.scala 32:10]
    node div__T_501 = mux(div__T_495, UInt<2>("h3"), div__T_500) @[CircuitMath.scala 32:10]
    node div__T_502 = mux(div__T_487, div__T_494, div__T_501) @[CircuitMath.scala 38:21]
    node div__T_503 = cat(div__T_487, div__T_502) @[Cat.scala 30:58]
    node div__T_504 = mux(div__T_463, div__T_483, div__T_503) @[CircuitMath.scala 38:21]
    node div__T_505 = cat(div__T_463, div__T_504) @[Cat.scala 30:58]
    node div__T_506 = bits(div__T_457, 15, 8) @[CircuitMath.scala 35:17]
    node div__T_507 = bits(div__T_457, 7, 0) @[CircuitMath.scala 36:17]
    node div__T_509 = neq(div__T_506, UInt<8>("h0")) @[CircuitMath.scala 37:22]
    node div__T_510 = bits(div__T_506, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_511 = bits(div__T_506, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_513 = neq(div__T_510, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_514 = bits(div__T_510, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_516 = bits(div__T_510, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_518 = bits(div__T_510, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_519 = mux(div__T_516, UInt<2>("h2"), pad(div__T_518, 2)) @[CircuitMath.scala 32:10]
    node div__T_520 = mux(div__T_514, UInt<2>("h3"), div__T_519) @[CircuitMath.scala 32:10]
    node div__T_521 = bits(div__T_511, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_523 = bits(div__T_511, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_525 = bits(div__T_511, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_526 = mux(div__T_523, UInt<2>("h2"), pad(div__T_525, 2)) @[CircuitMath.scala 32:10]
    node div__T_527 = mux(div__T_521, UInt<2>("h3"), div__T_526) @[CircuitMath.scala 32:10]
    node div__T_528 = mux(div__T_513, div__T_520, div__T_527) @[CircuitMath.scala 38:21]
    node div__T_529 = cat(div__T_513, div__T_528) @[Cat.scala 30:58]
    node div__T_530 = bits(div__T_507, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_531 = bits(div__T_507, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_533 = neq(div__T_530, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_534 = bits(div__T_530, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_536 = bits(div__T_530, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_538 = bits(div__T_530, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_539 = mux(div__T_536, UInt<2>("h2"), pad(div__T_538, 2)) @[CircuitMath.scala 32:10]
    node div__T_540 = mux(div__T_534, UInt<2>("h3"), div__T_539) @[CircuitMath.scala 32:10]
    node div__T_541 = bits(div__T_531, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_543 = bits(div__T_531, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_545 = bits(div__T_531, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_546 = mux(div__T_543, UInt<2>("h2"), pad(div__T_545, 2)) @[CircuitMath.scala 32:10]
    node div__T_547 = mux(div__T_541, UInt<2>("h3"), div__T_546) @[CircuitMath.scala 32:10]
    node div__T_548 = mux(div__T_533, div__T_540, div__T_547) @[CircuitMath.scala 38:21]
    node div__T_549 = cat(div__T_533, div__T_548) @[Cat.scala 30:58]
    node div__T_550 = mux(div__T_509, div__T_529, div__T_549) @[CircuitMath.scala 38:21]
    node div__T_551 = cat(div__T_509, div__T_550) @[Cat.scala 30:58]
    node div__T_552 = mux(div__T_459, div__T_505, div__T_551) @[CircuitMath.scala 38:21]
    node div__T_553 = cat(div__T_459, div__T_552) @[Cat.scala 30:58]
    node div__T_554 = bits(div__T_453, 31, 16) @[CircuitMath.scala 35:17]
    node div__T_555 = bits(div__T_453, 15, 0) @[CircuitMath.scala 36:17]
    node div__T_557 = neq(div__T_554, UInt<16>("h0")) @[CircuitMath.scala 37:22]
    node div__T_558 = bits(div__T_554, 15, 8) @[CircuitMath.scala 35:17]
    node div__T_559 = bits(div__T_554, 7, 0) @[CircuitMath.scala 36:17]
    node div__T_561 = neq(div__T_558, UInt<8>("h0")) @[CircuitMath.scala 37:22]
    node div__T_562 = bits(div__T_558, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_563 = bits(div__T_558, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_565 = neq(div__T_562, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_566 = bits(div__T_562, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_568 = bits(div__T_562, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_570 = bits(div__T_562, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_571 = mux(div__T_568, UInt<2>("h2"), pad(div__T_570, 2)) @[CircuitMath.scala 32:10]
    node div__T_572 = mux(div__T_566, UInt<2>("h3"), div__T_571) @[CircuitMath.scala 32:10]
    node div__T_573 = bits(div__T_563, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_575 = bits(div__T_563, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_577 = bits(div__T_563, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_578 = mux(div__T_575, UInt<2>("h2"), pad(div__T_577, 2)) @[CircuitMath.scala 32:10]
    node div__T_579 = mux(div__T_573, UInt<2>("h3"), div__T_578) @[CircuitMath.scala 32:10]
    node div__T_580 = mux(div__T_565, div__T_572, div__T_579) @[CircuitMath.scala 38:21]
    node div__T_581 = cat(div__T_565, div__T_580) @[Cat.scala 30:58]
    node div__T_582 = bits(div__T_559, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_583 = bits(div__T_559, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_585 = neq(div__T_582, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_586 = bits(div__T_582, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_588 = bits(div__T_582, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_590 = bits(div__T_582, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_591 = mux(div__T_588, UInt<2>("h2"), pad(div__T_590, 2)) @[CircuitMath.scala 32:10]
    node div__T_592 = mux(div__T_586, UInt<2>("h3"), div__T_591) @[CircuitMath.scala 32:10]
    node div__T_593 = bits(div__T_583, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_595 = bits(div__T_583, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_597 = bits(div__T_583, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_598 = mux(div__T_595, UInt<2>("h2"), pad(div__T_597, 2)) @[CircuitMath.scala 32:10]
    node div__T_599 = mux(div__T_593, UInt<2>("h3"), div__T_598) @[CircuitMath.scala 32:10]
    node div__T_600 = mux(div__T_585, div__T_592, div__T_599) @[CircuitMath.scala 38:21]
    node div__T_601 = cat(div__T_585, div__T_600) @[Cat.scala 30:58]
    node div__T_602 = mux(div__T_561, div__T_581, div__T_601) @[CircuitMath.scala 38:21]
    node div__T_603 = cat(div__T_561, div__T_602) @[Cat.scala 30:58]
    node div__T_604 = bits(div__T_555, 15, 8) @[CircuitMath.scala 35:17]
    node div__T_605 = bits(div__T_555, 7, 0) @[CircuitMath.scala 36:17]
    node div__T_607 = neq(div__T_604, UInt<8>("h0")) @[CircuitMath.scala 37:22]
    node div__T_608 = bits(div__T_604, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_609 = bits(div__T_604, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_611 = neq(div__T_608, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_612 = bits(div__T_608, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_614 = bits(div__T_608, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_616 = bits(div__T_608, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_617 = mux(div__T_614, UInt<2>("h2"), pad(div__T_616, 2)) @[CircuitMath.scala 32:10]
    node div__T_618 = mux(div__T_612, UInt<2>("h3"), div__T_617) @[CircuitMath.scala 32:10]
    node div__T_619 = bits(div__T_609, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_621 = bits(div__T_609, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_623 = bits(div__T_609, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_624 = mux(div__T_621, UInt<2>("h2"), pad(div__T_623, 2)) @[CircuitMath.scala 32:10]
    node div__T_625 = mux(div__T_619, UInt<2>("h3"), div__T_624) @[CircuitMath.scala 32:10]
    node div__T_626 = mux(div__T_611, div__T_618, div__T_625) @[CircuitMath.scala 38:21]
    node div__T_627 = cat(div__T_611, div__T_626) @[Cat.scala 30:58]
    node div__T_628 = bits(div__T_605, 7, 4) @[CircuitMath.scala 35:17]
    node div__T_629 = bits(div__T_605, 3, 0) @[CircuitMath.scala 36:17]
    node div__T_631 = neq(div__T_628, UInt<4>("h0")) @[CircuitMath.scala 37:22]
    node div__T_632 = bits(div__T_628, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_634 = bits(div__T_628, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_636 = bits(div__T_628, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_637 = mux(div__T_634, UInt<2>("h2"), pad(div__T_636, 2)) @[CircuitMath.scala 32:10]
    node div__T_638 = mux(div__T_632, UInt<2>("h3"), div__T_637) @[CircuitMath.scala 32:10]
    node div__T_639 = bits(div__T_629, 3, 3) @[CircuitMath.scala 32:12]
    node div__T_641 = bits(div__T_629, 2, 2) @[CircuitMath.scala 32:12]
    node div__T_643 = bits(div__T_629, 1, 1) @[CircuitMath.scala 30:8]
    node div__T_644 = mux(div__T_641, UInt<2>("h2"), pad(div__T_643, 2)) @[CircuitMath.scala 32:10]
    node div__T_645 = mux(div__T_639, UInt<2>("h3"), div__T_644) @[CircuitMath.scala 32:10]
    node div__T_646 = mux(div__T_631, div__T_638, div__T_645) @[CircuitMath.scala 38:21]
    node div__T_647 = cat(div__T_631, div__T_646) @[Cat.scala 30:58]
    node div__T_648 = mux(div__T_607, div__T_627, div__T_647) @[CircuitMath.scala 38:21]
    node div__T_649 = cat(div__T_607, div__T_648) @[Cat.scala 30:58]
    node div__T_650 = mux(div__T_557, div__T_603, div__T_649) @[CircuitMath.scala 38:21]
    node div__T_651 = cat(div__T_557, div__T_650) @[Cat.scala 30:58]
    node div__T_652 = mux(div__T_455, div__T_553, div__T_651) @[CircuitMath.scala 38:21]
    node div__T_653 = cat(div__T_455, div__T_652) @[Cat.scala 30:58]
    node div__T_655 = add(UInt<6>("h3f"), div__T_450) @[Multiplier.scala 138:31]
    node div__T_656 = tail(div__T_655, 1) @[Multiplier.scala 138:31]
    node div__T_657 = sub(div__T_656, div__T_653) @[Multiplier.scala 138:44]
    skip
    node div__T_659 = tail(div__T_657, 1) @[Multiplier.scala 138:44]
    node div__T_660 = gt(div__T_450, div__T_653) @[Multiplier.scala 139:33]
    skip
    node div__T_664 = not(div__T_247) @[Multiplier.scala 140:33]
    node div__T_665 = and(div__T_243, div__T_664) @[Multiplier.scala 140:30]
    node div__T_667 = geq(div__T_659, UInt<6>("h1")) @[Multiplier.scala 140:53]
    node div__T_668 = or(div__T_667, div__T_660) @[Multiplier.scala 140:70]
    node div__T_669 = and(div__T_665, div__T_668) @[Multiplier.scala 140:41]
    node div__T_671 = mux(div__T_660, UInt<6>("h3f"), div__T_659) @[Multiplier.scala 142:22]
    skip
    skip
    skip
    node div__T_675 = dshl(div__T_147, div__T_671) @[Multiplier.scala 144:39]
    node div__GEN_14 = mux(div__T_669, pad(div__T_675, 129), div__T_234) @[Multiplier.scala 126:15 141:19 144:19]
    node div__GEN_15 = mux(div__T_669, pad(div__T_671, 7), div__T_217) @[Multiplier.scala 132:11 141:19 145:15]
    skip
    node div__T_678 = and(div__T_247, div__T_191) @[Multiplier.scala 148:18]
    node div__GEN_16 = mux(div__T_678, UInt<1>("h0"), div_neg_out) @[Multiplier.scala 148:{28,38} 49:20]
    node div__GEN_17 = mux(div__T_225, pad(div__GEN_14, 130), div__GEN_10) @[Multiplier.scala 118:37]
    node div__GEN_18 = mux(div__T_225, div__GEN_13, div__GEN_12) @[Multiplier.scala 118:37]
    node div__GEN_19 = mux(div__T_225, div__GEN_15, div__GEN_11) @[Multiplier.scala 118:37]
    node div__GEN_20 = mux(div__T_225, div__GEN_16, div_neg_out) @[Multiplier.scala 118:37 49:20]
    node dmem_resp_valid = and(io_dmem_resp_valid, io_dmem_resp_bits_has_data) @[Rocket.scala 426:44]
    node dmem_resp_replay = and(dmem_resp_valid, io_dmem_resp_bits_replay) @[Rocket.scala 427:42]
    node _T_4176 = bits(io_dmem_resp_bits_tag, 0, 0) @[Rocket.scala 423:45]
    skip
    node dmem_resp_xpu = not(_T_4176) @[Rocket.scala 423:23]
    node _T_4183 = and(dmem_resp_replay, dmem_resp_xpu) @[Rocket.scala 442:26]
    skip
    node div_io_resp_ready = mux(_T_4183, UInt<1>("h0"), _T_4415) @[Rocket.scala 429:21 442:44 443:23]
    skip
    node div__T_680 = and(div_io_resp_ready, div__T_708) @[Decoupled.scala 30:37]
    node _T_4146 = and(mem_reg_valid, mem_ctrl_wxd) @[Rocket.scala 392:39]
    node dcache_kill_mem = and(_T_4146, io_dmem_replay_next) @[Rocket.scala 392:55]
    node _T_4149 = or(dcache_kill_mem, take_pc_wb) @[Rocket.scala 395:38]
    reg mem_reg_xcpt : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_xcpt) @[Rocket.scala 137:36]
    node _T_4150 = or(_T_4149, mem_reg_xcpt) @[Rocket.scala 395:52]
    node _T_4152 = not(mem_reg_valid) @[Rocket.scala 395:71]
    node killm_common = or(_T_4150, _T_4152) @[Rocket.scala 395:68]
    reg _T_4154 : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), _T_4154) @[Rocket.scala 396:37]
    node div_io_kill = and(killm_common, _T_4154) @[Rocket.scala 396:31]
    skip
    node div__T_681 = or(div__T_680, div_io_kill) @[Multiplier.scala 150:24]
    node div__GEN_21 = mux(div__T_681, UInt<3>("h0"), div__GEN_18) @[Multiplier.scala 150:36 151:11]
    node div__T_682 = and(div__T_709, div_io_req_valid) @[Decoupled.scala 30:37]
    node div__T_684 = not(div__T_88) @[Multiplier.scala 154:42]
    node div__T_685 = and(div_rhs_sign, div__T_684) @[Multiplier.scala 154:39]
    node div__T_686 = or(div_lhs_sign, div__T_685) @[Multiplier.scala 154:27]
    node div__T_687 = mux(div__T_686, UInt<3>("h1"), UInt<3>("h2")) @[Multiplier.scala 154:17]
    skip
    node div__T_691 = neq(div_lhs_sign, div_rhs_sign) @[Multiplier.scala 158:57]
    node div__T_692 = mux(div__T_100, div_lhs_sign, div__T_691) @[Multiplier.scala 158:30]
    node div__T_693 = and(div__T_684, div__T_692) @[Multiplier.scala 158:24]
    node div__T_694 = cat(div_rhs_sign, div_rhs_in) @[Cat.scala 30:58]
    node div__GEN_22 = mux(div__T_682, div__T_687, div__GEN_21) @[Multiplier.scala 153:24 154:11]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    node div__T_697 = not(div_req_dw) @[Multiplier.scala 67:62]
    skip
    node div__T_699 = bits(div_remainder, 31, 31) @[Multiplier.scala 165:67]
    skip
    node div__T_703 = mux(div__T_699, UInt<32>("hffffffff"), UInt<32>("h0")) @[Bitwise.scala 71:12]
    node div__T_704 = bits(div_remainder, 31, 0) @[Multiplier.scala 165:86]
    node div__T_705 = cat(div__T_703, div__T_704) @[Cat.scala 30:58]
    skip
    node div__T_707 = mux(div__T_697, div__T_705, div__T_147) @[Multiplier.scala 165:27]
    skip
    reg ex_ctrl_branch : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_branch) @[Rocket.scala 115:20]
    reg ex_ctrl_jal : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_jal) @[Rocket.scala 115:20]
    reg ex_ctrl_rxs2 : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_rxs2) @[Rocket.scala 115:20]
    skip
    reg ex_ctrl_mem_cmd : UInt<5>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_mem_cmd) @[Rocket.scala 115:20]
    reg ex_ctrl_mem_type : UInt<3>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_mem_type) @[Rocket.scala 115:20]
    skip
    skip
    skip
    reg ex_ctrl_fence_i : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_ctrl_fence_i) @[Rocket.scala 115:20]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    reg mem_ctrl_fence_i : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_ctrl_fence_i) @[Rocket.scala 116:21]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    reg wb_ctrl_fence_i : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), wb_ctrl_fence_i) @[Rocket.scala 117:20]
    skip
    skip
    skip
    reg ex_reg_btb_hit : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_btb_hit) @[Rocket.scala 122:35]
    reg ex_reg_btb_resp_taken : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_btb_resp_taken) @[Rocket.scala 123:35]
    reg ex_reg_btb_resp_mask : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_btb_resp_mask) @[Rocket.scala 123:35]
    reg ex_reg_btb_resp_bridx : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_btb_resp_bridx) @[Rocket.scala 123:35]
    reg ex_reg_btb_resp_target : UInt<39>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_btb_resp_target) @[Rocket.scala 123:35]
    reg ex_reg_btb_resp_entry : UInt<6>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_btb_resp_entry) @[Rocket.scala 123:35]
    reg ex_reg_btb_resp_bht_history : UInt<7>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_btb_resp_bht_history) @[Rocket.scala 123:35]
    reg ex_reg_btb_resp_bht_value : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_btb_resp_bht_value) @[Rocket.scala 123:35]
    reg ex_reg_xcpt : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_xcpt) @[Rocket.scala 124:35]
    reg ex_reg_flush_pipe : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_flush_pipe) @[Rocket.scala 125:35]
    reg ex_reg_load_use : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), ex_reg_load_use) @[Rocket.scala 126:35]
    reg ex_cause : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), ex_cause) @[Rocket.scala 127:35]
    reg mem_reg_xcpt_interrupt : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_xcpt_interrupt) @[Rocket.scala 132:36]
    reg mem_reg_btb_hit : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_btb_hit) @[Rocket.scala 135:36]
    reg mem_reg_btb_resp_taken : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_btb_resp_taken) @[Rocket.scala 136:36]
    reg mem_reg_btb_resp_mask : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_btb_resp_mask) @[Rocket.scala 136:36]
    reg mem_reg_btb_resp_bridx : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_btb_resp_bridx) @[Rocket.scala 136:36]
    reg mem_reg_btb_resp_target : UInt<39>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_btb_resp_target) @[Rocket.scala 136:36]
    reg mem_reg_btb_resp_entry : UInt<6>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_btb_resp_entry) @[Rocket.scala 136:36]
    reg mem_reg_btb_resp_bht_history : UInt<7>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_btb_resp_bht_history) @[Rocket.scala 136:36]
    reg mem_reg_btb_resp_bht_value : UInt<2>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_btb_resp_bht_value) @[Rocket.scala 136:36]
    reg mem_reg_replay : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_replay) @[Rocket.scala 138:36]
    reg mem_reg_cause : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_cause) @[Rocket.scala 140:36]
    reg mem_reg_load : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_load) @[Rocket.scala 142:36]
    reg mem_reg_store : UInt<1>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_store) @[Rocket.scala 143:36]
    reg mem_reg_rs2 : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), mem_reg_rs2) @[Rocket.scala 147:24]
    skip
    node _T_2607 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h106f")) @[Decode.scala 13:65]
    node _T_2609 = eq(_T_2607, UInt<32>("h3")) @[Decode.scala 13:121]
    node _T_2611 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h607f")) @[Decode.scala 13:65]
    node _T_2613 = eq(_T_2611, UInt<32>("hf")) @[Decode.scala 13:121]
    node _T_2615 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h7077")) @[Decode.scala 13:65]
    node _T_2617 = eq(_T_2615, UInt<32>("h13")) @[Decode.scala 13:121]
    node _T_2619 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h5f")) @[Decode.scala 13:65]
    node _T_2621 = eq(_T_2619, UInt<32>("h17")) @[Decode.scala 13:121]
    node _T_2623 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hfc00007f")) @[Decode.scala 13:65]
    node _T_2625 = eq(_T_2623, UInt<32>("h33")) @[Decode.scala 13:121]
    node _T_2627 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hbe007077")) @[Decode.scala 13:65]
    node _T_2629 = eq(_T_2627, UInt<32>("h33")) @[Decode.scala 13:121]
    node _T_2631 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h4000073")) @[Decode.scala 13:65]
    node _T_2633 = eq(_T_2631, UInt<32>("h43")) @[Decode.scala 13:121]
    node _T_2635 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("he400007f")) @[Decode.scala 13:65]
    node _T_2637 = eq(_T_2635, UInt<32>("h53")) @[Decode.scala 13:121]
    node _T_2639 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h707b")) @[Decode.scala 13:65]
    node _T_2641 = eq(_T_2639, UInt<32>("h63")) @[Decode.scala 13:121]
    node _T_2643 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h7f")) @[Decode.scala 13:65]
    node _T_2645 = eq(_T_2643, UInt<32>("h6f")) @[Decode.scala 13:121]
    node _T_2647 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hffefffff")) @[Decode.scala 13:65]
    node _T_2649 = eq(_T_2647, UInt<32>("h73")) @[Decode.scala 13:121]
    node _T_2651 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hfc00305f")) @[Decode.scala 13:65]
    node _T_2653 = eq(_T_2651, UInt<32>("h1013")) @[Decode.scala 13:121]
    node _T_2655 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hfe00305f")) @[Decode.scala 13:65]
    node _T_2657 = eq(_T_2655, UInt<32>("h101b")) @[Decode.scala 13:121]
    skip
    node _T_2665 = eq(_T_2603, UInt<32>("h2013")) @[Decode.scala 13:121]
    skip
    node _T_2673 = eq(_T_2603, UInt<32>("h2073")) @[Decode.scala 13:121]
    node _T_2675 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hbc00707f")) @[Decode.scala 13:65]
    node _T_2677 = eq(_T_2675, UInt<32>("h5013")) @[Decode.scala 13:121]
    node _T_2679 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hbe00705f")) @[Decode.scala 13:65]
    node _T_2681 = eq(_T_2679, UInt<32>("h501b")) @[Decode.scala 13:121]
    skip
    node _T_2685 = eq(_T_2627, UInt<32>("h5033")) @[Decode.scala 13:121]
    node _T_2687 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hfe004077")) @[Decode.scala 13:65]
    node _T_2689 = eq(_T_2687, UInt<32>("h2004033")) @[Decode.scala 13:121]
    node _T_2699 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hdfffffff")) @[Decode.scala 13:65]
    node _T_2701 = eq(_T_2699, UInt<32>("h10200073")) @[Decode.scala 13:121]
    node _T_2703 = eq(ibuf_RVCExpander__T_1859_bits, UInt<32>("h10500073")) @[Decode.scala 13:121]
    node _T_2705 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hfe007fff")) @[Decode.scala 13:65]
    node _T_2707 = eq(_T_2705, UInt<32>("h12000073")) @[Decode.scala 13:121]
    node _T_2709 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hf400607f")) @[Decode.scala 13:65]
    node _T_2711 = eq(_T_2709, UInt<32>("h20000053")) @[Decode.scala 13:121]
    node _T_2713 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h7c00607f")) @[Decode.scala 13:65]
    node _T_2715 = eq(_T_2713, UInt<32>("h20000053")) @[Decode.scala 13:121]
    node _T_2717 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h7c00507f")) @[Decode.scala 13:65]
    node _T_2719 = eq(_T_2717, UInt<32>("h20000053")) @[Decode.scala 13:121]
    node _T_2721 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h7ff0007f")) @[Decode.scala 13:65]
    node _T_2723 = eq(_T_2721, UInt<32>("h40100053")) @[Decode.scala 13:121]
    skip
    node _T_2727 = eq(_T_2721, UInt<32>("h42000053")) @[Decode.scala 13:121]
    node _T_2729 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hfdf0007f")) @[Decode.scala 13:65]
    node _T_2731 = eq(_T_2729, UInt<32>("h58000053")) @[Decode.scala 13:121]
    node _T_2733 = eq(ibuf_RVCExpander__T_1859_bits, UInt<32>("h7b200073")) @[Decode.scala 13:121]
    node _T_2735 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hedc0007f")) @[Decode.scala 13:65]
    node _T_2737 = eq(_T_2735, UInt<32>("hc0000053")) @[Decode.scala 13:121]
    node _T_2739 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hfdf0607f")) @[Decode.scala 13:65]
    node _T_2741 = eq(_T_2739, UInt<32>("he0000053")) @[Decode.scala 13:121]
    node _T_2743 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hedf0707f")) @[Decode.scala 13:65]
    node _T_2745 = eq(_T_2743, UInt<32>("he0000053")) @[Decode.scala 13:121]
    node _T_2747 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h603f")) @[Decode.scala 13:65]
    node _T_2749 = eq(_T_2747, UInt<32>("h23")) @[Decode.scala 13:121]
    node _T_2751 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h306f")) @[Decode.scala 13:65]
    node _T_2753 = eq(_T_2751, UInt<32>("h1063")) @[Decode.scala 13:121]
    node _T_2755 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h407f")) @[Decode.scala 13:65]
    node _T_2757 = eq(_T_2755, UInt<32>("h4063")) @[Decode.scala 13:121]
    node _T_2759 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hfc007077")) @[Decode.scala 13:65]
    node _T_2761 = eq(_T_2759, UInt<32>("h33")) @[Decode.scala 13:121]
    skip
    node _T_2764 = or(_T_2605, _T_2609) @[Decode.scala 14:30]
    node _T_2765 = or(_T_2764, _T_2613) @[Decode.scala 14:30]
    node _T_2766 = or(_T_2765, _T_2617) @[Decode.scala 14:30]
    node _T_2767 = or(_T_2766, _T_2621) @[Decode.scala 14:30]
    node _T_2768 = or(_T_2767, _T_2625) @[Decode.scala 14:30]
    node _T_2769 = or(_T_2768, _T_2629) @[Decode.scala 14:30]
    node _T_2770 = or(_T_2769, _T_2633) @[Decode.scala 14:30]
    node _T_2771 = or(_T_2770, _T_2637) @[Decode.scala 14:30]
    node _T_2772 = or(_T_2771, _T_2641) @[Decode.scala 14:30]
    node _T_2773 = or(_T_2772, _T_2645) @[Decode.scala 14:30]
    node _T_2774 = or(_T_2773, _T_2649) @[Decode.scala 14:30]
    node _T_2775 = or(_T_2774, _T_2653) @[Decode.scala 14:30]
    node _T_2776 = or(_T_2775, _T_2657) @[Decode.scala 14:30]
    node _T_2777 = or(_T_2776, _T_2661) @[Decode.scala 14:30]
    node _T_2778 = or(_T_2777, _T_2665) @[Decode.scala 14:30]
    node _T_2779 = or(_T_2778, _T_2669) @[Decode.scala 14:30]
    node _T_2780 = or(_T_2779, _T_2673) @[Decode.scala 14:30]
    node _T_2781 = or(_T_2780, _T_2677) @[Decode.scala 14:30]
    node _T_2782 = or(_T_2781, _T_2681) @[Decode.scala 14:30]
    node _T_2783 = or(_T_2782, _T_2685) @[Decode.scala 14:30]
    node _T_2784 = or(_T_2783, _T_2689) @[Decode.scala 14:30]
    node _T_2785 = or(_T_2784, _T_2693) @[Decode.scala 14:30]
    node _T_2786 = or(_T_2785, _T_2697) @[Decode.scala 14:30]
    node _T_2787 = or(_T_2786, _T_2701) @[Decode.scala 14:30]
    node _T_2788 = or(_T_2787, _T_2703) @[Decode.scala 14:30]
    node _T_2789 = or(_T_2788, _T_2707) @[Decode.scala 14:30]
    node _T_2790 = or(_T_2789, _T_2711) @[Decode.scala 14:30]
    node _T_2791 = or(_T_2790, _T_2715) @[Decode.scala 14:30]
    node _T_2792 = or(_T_2791, _T_2719) @[Decode.scala 14:30]
    node _T_2793 = or(_T_2792, _T_2723) @[Decode.scala 14:30]
    node _T_2794 = or(_T_2793, _T_2727) @[Decode.scala 14:30]
    node _T_2795 = or(_T_2794, _T_2731) @[Decode.scala 14:30]
    node _T_2796 = or(_T_2795, _T_2733) @[Decode.scala 14:30]
    node _T_2797 = or(_T_2796, _T_2737) @[Decode.scala 14:30]
    node _T_2798 = or(_T_2797, _T_2741) @[Decode.scala 14:30]
    node _T_2799 = or(_T_2798, _T_2745) @[Decode.scala 14:30]
    node _T_2800 = or(_T_2799, _T_2749) @[Decode.scala 14:30]
    node _T_2801 = or(_T_2800, _T_2753) @[Decode.scala 14:30]
    node _T_2802 = or(_T_2801, _T_2757) @[Decode.scala 14:30]
    node id_ctrl_legal = or(_T_2802, _T_2761) @[Decode.scala 14:30]
    node _T_2817 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h74")) @[Decode.scala 13:65]
    node id_ctrl_branch = eq(_T_2817, UInt<32>("h60")) @[Decode.scala 13:121]
    skip
    node _T_2829 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h203c")) @[Decode.scala 13:65]
    node id_ctrl_jalr = eq(_T_2829, UInt<32>("h24")) @[Decode.scala 13:121]
    skip
    node _T_2882 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h58")) @[Decode.scala 13:65]
    node _T_2884 = eq(_T_2882, UInt<32>("h0")) @[Decode.scala 13:121]
    node _T_2886 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h20")) @[Decode.scala 13:65]
    node _T_2888 = eq(_T_2886, UInt<32>("h0")) @[Decode.scala 13:121]
    node _T_2890 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hc")) @[Decode.scala 13:65]
    node _T_2892 = eq(_T_2890, UInt<32>("h4")) @[Decode.scala 13:121]
    node _T_2894 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h48")) @[Decode.scala 13:65]
    node _T_2896 = eq(_T_2894, UInt<32>("h48")) @[Decode.scala 13:121]
    node _T_2898 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h4050")) @[Decode.scala 13:65]
    node _T_2900 = eq(_T_2898, UInt<32>("h4050")) @[Decode.scala 13:121]
    skip
    node _T_2903 = or(_T_2884, _T_2888) @[Decode.scala 14:30]
    node _T_2904 = or(_T_2903, _T_2892) @[Decode.scala 14:30]
    node _T_2905 = or(_T_2904, _T_2896) @[Decode.scala 14:30]
    node _T_2906 = or(_T_2905, _T_2900) @[Decode.scala 14:30]
    skip
    node _T_2910 = eq(_T_2894, UInt<32>("h0")) @[Decode.scala 13:121]
    node _T_2912 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h18")) @[Decode.scala 13:65]
    node _T_2914 = eq(_T_2912, UInt<32>("h0")) @[Decode.scala 13:121]
    node _T_2916 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h4008")) @[Decode.scala 13:65]
    node _T_2918 = eq(_T_2916, UInt<32>("h4000")) @[Decode.scala 13:121]
    skip
    node _T_2921 = or(_T_2910, _T_2858) @[Decode.scala 14:30]
    node _T_2922 = or(_T_2921, _T_2914) @[Decode.scala 14:30]
    node _T_2923 = or(_T_2922, _T_2918) @[Decode.scala 14:30]
    node id_ctrl_sel_alu2 = cat(_T_2923, _T_2906) @[Cat.scala 30:58]
    node _T_2926 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h4004")) @[Decode.scala 13:65]
    node _T_2928 = eq(_T_2926, UInt<32>("h0")) @[Decode.scala 13:121]
    skip
    node _T_2932 = eq(_T_3242, UInt<32>("h0")) @[Decode.scala 13:121]
    node _T_2934 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h24")) @[Decode.scala 13:65]
    node _T_2936 = eq(_T_2934, UInt<32>("h0")) @[Decode.scala 13:121]
    skip
    node _T_2939 = or(_T_2928, _T_2932) @[Decode.scala 14:30]
    node _T_2940 = or(_T_2939, _T_2858) @[Decode.scala 14:30]
    node _T_2941 = or(_T_2940, _T_2936) @[Decode.scala 14:30]
    node _T_2942 = or(_T_2941, _T_2914) @[Decode.scala 14:30]
    skip
    node _T_2946 = eq(_T_2839, UInt<32>("h14")) @[Decode.scala 13:121]
    skip
    node _T_2949 = or(_T_2946, _T_2896) @[Decode.scala 14:30]
    node id_ctrl_sel_alu1 = cat(_T_2949, _T_2942) @[Cat.scala 30:58]
    skip
    node _T_2954 = eq(_T_2912, UInt<32>("h8")) @[Decode.scala 13:121]
    skip
    node _T_2958 = eq(_T_2856, UInt<32>("h40")) @[Decode.scala 13:121]
    skip
    node _T_2961 = or(_T_2954, _T_2958) @[Decode.scala 14:30]
    node _T_2963 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h14")) @[Decode.scala 13:65]
    node _T_2965 = eq(_T_2963, UInt<32>("h14")) @[Decode.scala 13:121]
    skip
    node _T_2968 = or(_T_2954, _T_2965) @[Decode.scala 14:30]
    node _T_2970 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h30")) @[Decode.scala 13:65]
    node _T_2972 = eq(_T_2970, UInt<32>("h0")) @[Decode.scala 13:121]
    node _T_2974 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h201c")) @[Decode.scala 13:65]
    node _T_2976 = eq(_T_2974, UInt<32>("h4")) @[Decode.scala 13:121]
    skip
    node _T_2980 = eq(_T_2963, UInt<32>("h10")) @[Decode.scala 13:121]
    skip
    node _T_2983 = or(_T_2972, _T_2976) @[Decode.scala 14:30]
    node _T_2984 = or(_T_2983, _T_2980) @[Decode.scala 14:30]
    node _T_2985 = cat(_T_2984, _T_2968) @[Cat.scala 30:58]
    node id_ctrl_sel_imm = cat(_T_2985, _T_2961) @[Cat.scala 30:58]
    node _T_2988 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h10")) @[Decode.scala 13:65]
    node _T_2990 = eq(_T_2988, UInt<32>("h0")) @[Decode.scala 13:121]
    node _T_2992 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h8")) @[Decode.scala 13:65]
    node _T_2994 = eq(_T_2992, UInt<32>("h0")) @[Decode.scala 13:121]
    skip
    node id_ctrl_alu_dw = or(_T_2990, _T_2994) @[Decode.scala 14:30]
    node _T_2999 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h3054")) @[Decode.scala 13:65]
    node _T_3001 = eq(_T_2999, UInt<32>("h1010")) @[Decode.scala 13:121]
    node _T_3003 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h1058")) @[Decode.scala 13:65]
    node _T_3005 = eq(_T_3003, UInt<32>("h1040")) @[Decode.scala 13:121]
    node _T_3007 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h7044")) @[Decode.scala 13:65]
    node _T_3009 = eq(_T_3007, UInt<32>("h7000")) @[Decode.scala 13:121]
    skip
    node _T_3012 = or(_T_3001, _T_3005) @[Decode.scala 14:30]
    node _T_3013 = or(_T_3012, _T_3009) @[Decode.scala 14:30]
    node _T_3015 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h4054")) @[Decode.scala 13:65]
    node _T_3017 = eq(_T_3015, UInt<32>("h40")) @[Decode.scala 13:121]
    node _T_3019 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h2058")) @[Decode.scala 13:65]
    node _T_3021 = eq(_T_3019, UInt<32>("h2040")) @[Decode.scala 13:121]
    skip
    node _T_3025 = eq(_T_2999, UInt<32>("h3010")) @[Decode.scala 13:121]
    node _T_3027 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h6054")) @[Decode.scala 13:65]
    node _T_3029 = eq(_T_3027, UInt<32>("h6010")) @[Decode.scala 13:121]
    node _T_3031 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h40003034")) @[Decode.scala 13:65]
    node _T_3033 = eq(_T_3031, UInt<32>("h40000030")) @[Decode.scala 13:121]
    node _T_3035 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h40001054")) @[Decode.scala 13:65]
    node _T_3037 = eq(_T_3035, UInt<32>("h40001010")) @[Decode.scala 13:121]
    skip
    node _T_3040 = or(_T_3017, _T_3021) @[Decode.scala 14:30]
    node _T_3041 = or(_T_3040, _T_3025) @[Decode.scala 14:30]
    node _T_3042 = or(_T_3041, _T_3029) @[Decode.scala 14:30]
    node _T_3043 = or(_T_3042, _T_3033) @[Decode.scala 14:30]
    node _T_3044 = or(_T_3043, _T_3037) @[Decode.scala 14:30]
    node _T_3046 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h2054")) @[Decode.scala 13:65]
    node _T_3048 = eq(_T_3046, UInt<32>("h2010")) @[Decode.scala 13:121]
    node _T_3050 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h40004054")) @[Decode.scala 13:65]
    node _T_3052 = eq(_T_3050, UInt<32>("h4010")) @[Decode.scala 13:121]
    node _T_3054 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h5054")) @[Decode.scala 13:65]
    node _T_3056 = eq(_T_3054, UInt<32>("h4010")) @[Decode.scala 13:121]
    node _T_3058 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h4058")) @[Decode.scala 13:65]
    node _T_3060 = eq(_T_3058, UInt<32>("h4040")) @[Decode.scala 13:121]
    skip
    node _T_3063 = or(_T_3048, _T_3052) @[Decode.scala 14:30]
    node _T_3064 = or(_T_3063, _T_3056) @[Decode.scala 14:30]
    node _T_3065 = or(_T_3064, _T_3060) @[Decode.scala 14:30]
    skip
    node _T_3069 = eq(_T_3027, UInt<32>("h2010")) @[Decode.scala 13:121]
    node _T_3071 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h40003054")) @[Decode.scala 13:65]
    node _T_3073 = eq(_T_3071, UInt<32>("h40001010")) @[Decode.scala 13:121]
    skip
    node _T_3076 = or(_T_3069, _T_3060) @[Decode.scala 14:30]
    node _T_3077 = or(_T_3076, _T_3033) @[Decode.scala 14:30]
    node _T_3078 = or(_T_3077, _T_3073) @[Decode.scala 14:30]
    node _T_3079 = cat(_T_3044, _T_3013) @[Cat.scala 30:58]
    node _T_3080 = cat(_T_3078, _T_3065) @[Cat.scala 30:58]
    node id_ctrl_alu_fn = cat(_T_3080, _T_3079) @[Cat.scala 30:58]
    node _T_3104 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h2008")) @[Decode.scala 13:65]
    node _T_3106 = eq(_T_3104, UInt<32>("h8")) @[Decode.scala 13:121]
    skip
    node _T_3110 = eq(_T_3250, UInt<32>("h20")) @[Decode.scala 13:121]
    node _T_3112 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h18000020")) @[Decode.scala 13:65]
    node _T_3114 = eq(_T_3112, UInt<32>("h18000020")) @[Decode.scala 13:121]
    node _T_3116 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h20000020")) @[Decode.scala 13:65]
    node _T_3118 = eq(_T_3116, UInt<32>("h20000020")) @[Decode.scala 13:121]
    skip
    node _T_3121 = or(_T_3106, _T_3110) @[Decode.scala 14:30]
    node _T_3122 = or(_T_3121, _T_3114) @[Decode.scala 14:30]
    node _T_3123 = or(_T_3122, _T_3118) @[Decode.scala 14:30]
    node _T_3125 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h10002008")) @[Decode.scala 13:65]
    node _T_3127 = eq(_T_3125, UInt<32>("h10002008")) @[Decode.scala 13:121]
    node _T_3129 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h40002008")) @[Decode.scala 13:65]
    node _T_3131 = eq(_T_3129, UInt<32>("h40002008")) @[Decode.scala 13:121]
    skip
    node _T_3134 = or(_T_3127, _T_3131) @[Decode.scala 14:30]
    node _T_3136 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h8000008")) @[Decode.scala 13:65]
    node _T_3138 = eq(_T_3136, UInt<32>("h8000008")) @[Decode.scala 13:121]
    node _T_3140 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h10000008")) @[Decode.scala 13:65]
    node _T_3142 = eq(_T_3140, UInt<32>("h10000008")) @[Decode.scala 13:121]
    node _T_3144 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h80000008")) @[Decode.scala 13:65]
    node _T_3146 = eq(_T_3144, UInt<32>("h80000008")) @[Decode.scala 13:121]
    skip
    node _T_3149 = or(_T_3106, _T_3138) @[Decode.scala 14:30]
    node _T_3150 = or(_T_3149, _T_3142) @[Decode.scala 14:30]
    node _T_3151 = or(_T_3150, _T_3146) @[Decode.scala 14:30]
    node _T_3153 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h18002008")) @[Decode.scala 13:65]
    node _T_3155 = eq(_T_3153, UInt<32>("h2008")) @[Decode.scala 13:121]
    skip
    node _T_3159 = cat(_T_3134, _T_3123) @[Cat.scala 30:58]
    node _T_3160 = cat(UInt<1>("h0"), _T_3155) @[Cat.scala 30:58]
    node _T_3161 = cat(_T_3160, _T_3151) @[Cat.scala 30:58]
    node id_ctrl_mem_cmd = cat(_T_3161, _T_3159) @[Cat.scala 30:58]
    node _T_3164 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h1000")) @[Decode.scala 13:65]
    node _T_3166 = eq(_T_3164, UInt<32>("h1000")) @[Decode.scala 13:121]
    skip
    node _T_3170 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h2000")) @[Decode.scala 13:65]
    node _T_3172 = eq(_T_3170, UInt<32>("h2000")) @[Decode.scala 13:121]
    skip
    node _T_3176 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h4000")) @[Decode.scala 13:65]
    node _T_3178 = eq(_T_3176, UInt<32>("h4000")) @[Decode.scala 13:121]
    skip
    node _T_3181 = cat(_T_3178, _T_3172) @[Cat.scala 30:58]
    node id_ctrl_mem_type = cat(_T_3181, _T_3166) @[Cat.scala 30:58]
    node _T_3184 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h80000060")) @[Decode.scala 13:65]
    node _T_3186 = eq(_T_3184, UInt<32>("h40")) @[Decode.scala 13:121]
    node _T_3188 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h10000060")) @[Decode.scala 13:65]
    skip
    node _T_3192 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h70")) @[Decode.scala 13:65]
    node id_ctrl_rfs3 = eq(_T_3192, UInt<32>("h40")) @[Decode.scala 13:121]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    node _T_3219 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h3c")) @[Decode.scala 13:65]
    node _T_3221 = eq(_T_3219, UInt<32>("h4")) @[Decode.scala 13:121]
    skip
    node _T_3225 = eq(_T_3188, UInt<32>("h10000040")) @[Decode.scala 13:121]
    skip
    node _T_3228 = or(_T_3221, _T_3186) @[Decode.scala 14:30]
    node _T_3229 = or(_T_3228, id_ctrl_rfs3) @[Decode.scala 14:30]
    node id_ctrl_wfd = or(_T_3229, _T_3225) @[Decode.scala 14:30]
    node _T_3312 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h105c")) @[Decode.scala 13:65]
    node _T_3314 = eq(_T_3312, UInt<32>("h1004")) @[Decode.scala 13:121]
    node _T_3316 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("h2000060")) @[Decode.scala 13:65]
    node _T_3318 = eq(_T_3316, UInt<32>("h2000040")) @[Decode.scala 13:121]
    node _T_3320 = and(ibuf_RVCExpander__T_1859_bits, UInt<32>("hd0000070")) @[Decode.scala 13:65]
    node _T_3322 = eq(_T_3320, UInt<32>("h40000050")) @[Decode.scala 13:121]
    skip
    node _T_3325 = or(_T_3314, _T_3318) @[Decode.scala 14:30]
    node id_ctrl_dp = or(_T_3325, _T_3322) @[Decode.scala 14:30]
    node _T_3335 = eq(ibuf_RVCExpander__T_1859_rs1, UInt<5>("h0")) @[Rocket.scala 689:45]
    skip
    skip
    skip
    node _T_3341 = _T_3340 @[Rocket.scala 689:25]
    skip
    skip
    skip
    skip
    node _T_3351 = _T_3350 @[Rocket.scala 689:25]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    node id_system_insn = geq(id_ctrl_csr, UInt<3>("h4")) @[Rocket.scala 189:36]
    skip
    skip
    skip
    skip
    node id_csr_ren = and(_T_3453, _T_3335) @[Rocket.scala 190:54]
    node id_csr = mux(id_csr_ren, UInt<3>("h5"), id_ctrl_csr) @[Rocket.scala 191:19]
    node _T_3464 = not(id_csr_ren) @[Rocket.scala 192:54]
    node _T_3465 = and(id_csr_en, _T_3464) @[Rocket.scala 192:51]
    skip
    node _T_3466 = and(_T_3465, csr__T_2220) @[Rocket.scala 192:66]
    node id_csr_flush = or(id_system_insn, _T_3466) @[Rocket.scala 192:37]
    skip
    node _T_3468 = not(id_ctrl_legal) @[Rocket.scala 194:25]
    node _T_3469 = bits(csr_io_status_isa, 12, 12) @[Rocket.scala 195:38]
    node _T_3471 = not(_T_3469) @[Rocket.scala 195:20]
    node _T_3472 = and(id_ctrl_div, _T_3471) @[Rocket.scala 195:17]
    node _T_3473 = or(_T_3468, _T_3472) @[Rocket.scala 194:40]
    node _T_3474 = bits(csr_io_status_isa, 0, 0) @[Rocket.scala 196:38]
    node _T_3476 = not(_T_3474) @[Rocket.scala 196:20]
    node _T_3477 = and(id_ctrl_amo, _T_3476) @[Rocket.scala 196:17]
    node _T_3478 = or(_T_3473, _T_3477) @[Rocket.scala 195:48]
    node _T_3479 = or(csr__T_1764, io_fpu_illegal_rm) @[Rocket.scala 197:45]
    node _T_3480 = and(id_ctrl_fp, _T_3479) @[Rocket.scala 197:16]
    node _T_3481 = or(_T_3478, _T_3480) @[Rocket.scala 196:48]
    node _T_3482 = bits(csr_io_status_isa, 3, 3) @[Rocket.scala 198:37]
    node _T_3484 = not(_T_3482) @[Rocket.scala 198:19]
    skip
    node _T_3485 = and(id_ctrl_dp, _T_3484) @[Rocket.scala 198:16]
    node _T_3486 = or(_T_3481, _T_3485) @[Rocket.scala 197:67]
    node _T_3487 = bits(csr_io_status_isa, 2, 2) @[Rocket.scala 199:51]
    node _T_3489 = not(_T_3487) @[Rocket.scala 199:33]
    skip
    node _T_3490 = and(ibuf_RVCExpander__T_14, _T_3489) @[Rocket.scala 199:30]
    node _T_3491 = or(_T_3486, _T_3490) @[Rocket.scala 198:47]
    skip
    skip
    skip
    skip
    skip
    node _T_3496 = and(_T_3464, csr__T_2207) @[Rocket.scala 201:61]
    skip
    node _T_3497 = or(csr__T_2203, _T_3496) @[Rocket.scala 201:46]
    node _T_3498 = and(id_csr_en, _T_3497) @[Rocket.scala 201:15]
    node _T_3499 = or(_T_3491, _T_3498) @[Rocket.scala 200:48]
    skip
    node _T_3500 = and(id_system_insn, csr__T_2245) @[Rocket.scala 202:20]
    node id_illegal_insn = or(_T_3499, _T_3500) @[Rocket.scala 201:93]
    node id_amo_rl = bits(ibuf_RVCExpander__T_1859_bits, 25, 25) @[Rocket.scala 205:29]
    node _T_3501 = and(id_ctrl_amo, id_amo_rl) @[Rocket.scala 206:52]
    node id_fence_next = or(id_ctrl_fence, _T_3501) @[Rocket.scala 206:37]
    node _T_3511 = and(id_reg_fence, id_mem_busy) @[Rocket.scala 211:49]
    node _T_3512 = or(id_fence_next, _T_3511) @[Rocket.scala 211:33]
    skip
    skip
    node id_xcpt_if = or(ibuf__T_545, ibuf__T_553) @[Rocket.scala 221:45]
    skip
    node _T_3552 = or(csr__GEN_2, bpu__GEN_5) @[Rocket.scala 645:26]
    skip
    node _T_3553 = or(_T_3552, bpu__GEN_4) @[Rocket.scala 645:26]
    node _T_3554 = or(_T_3553, id_xcpt_if) @[Rocket.scala 645:26]
    node id_xcpt = or(_T_3554, id_illegal_insn) @[Rocket.scala 645:26]
    node _T_3555 = mux(id_xcpt_if, UInt<2>("h1"), UInt<2>("h2")) @[Mux.scala 31:69]
    node _T_3556 = mux(bpu__GEN_4, UInt<2>("h3"), _T_3555) @[Mux.scala 31:69]
    node _T_3557 = mux(bpu__GEN_5, UInt<4>("hd"), pad(_T_3556, 4)) @[Mux.scala 31:69]
    skip
    node id_cause = mux(csr__GEN_2, csr__GEN_3, pad(_T_3557, 64)) @[Mux.scala 31:69]
    node _T_3561 = and(ex_reg_valid, ex_ctrl_wxd) @[Rocket.scala 240:19]
    skip
    node _T_3564 = not(mem_ctrl_mem) @[Rocket.scala 241:39]
    node _T_3565 = and(_T_4146, _T_3564) @[Rocket.scala 241:36]
    skip
    node id_bypass_src_0_0 = eq(UInt<5>("h0"), ibuf_RVCExpander__T_1859_rs1) @[Rocket.scala 243:82]
    skip
    node _T_3568 = eq(ex_waddr, ibuf_RVCExpander__T_1859_rs1) @[Rocket.scala 243:82]
    node id_bypass_src_0_1 = and(_T_3561, _T_3568) @[Rocket.scala 243:74]
    node _T_3569 = eq(mem_waddr, ibuf_RVCExpander__T_1859_rs1) @[Rocket.scala 243:82]
    node id_bypass_src_0_2 = and(_T_3565, _T_3569) @[Rocket.scala 243:74]
    skip
    node id_bypass_src_0_3 = and(_T_4146, _T_3569) @[Rocket.scala 243:74]
    node id_bypass_src_1_0 = eq(UInt<5>("h0"), ibuf_RVCExpander__T_1859_rs2) @[Rocket.scala 243:82]
    skip
    node _T_3572 = eq(ex_waddr, ibuf_RVCExpander__T_1859_rs2) @[Rocket.scala 243:82]
    node id_bypass_src_1_1 = and(_T_3561, _T_3572) @[Rocket.scala 243:74]
    node _T_3573 = eq(mem_waddr, ibuf_RVCExpander__T_1859_rs2) @[Rocket.scala 243:82]
    node id_bypass_src_1_2 = and(_T_3565, _T_3573) @[Rocket.scala 243:74]
    skip
    node id_bypass_src_1_3 = and(_T_4146, _T_3573) @[Rocket.scala 243:74]
    skip
    node _T_3718 = not(take_pc_mem_wb) @[Rocket.scala 277:20]
    node _T_3719 = and(_T_3718, ibuf__T_543) @[Rocket.scala 277:29]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    node _T_3735 = not(bpu__GEN_4) @[Rocket.scala 293:13]
    node _T_3737 = not(ibuf__T_545) @[Rocket.scala 293:32]
    node _T_3738 = and(_T_3735, _T_3737) @[Rocket.scala 293:29]
    node _T_3739 = and(_T_3738, ibuf__T_553) @[Rocket.scala 293:58]
    node _GEN_16 = mux(_T_3739, UInt<2>("h1"), UInt<2>("h0")) @[Rocket.scala 292:24 293:87 294:26]
    node _GEN_17 = or(_T_3739, ibuf_RVCExpander__T_14) @[Rocket.scala 286:16 293:87 295:20]
    skip
    node _GEN_18 = mux(id_xcpt, UInt<4>("h0"), id_ctrl_alu_fn) @[Rocket.scala 285:13 288:20 289:22]
    skip
    node _GEN_19 = or(id_xcpt, id_ctrl_alu_dw) @[Rocket.scala 285:13 288:20 290:22]
    skip
    node _GEN_20 = mux(id_xcpt, UInt<2>("h2"), id_ctrl_sel_alu1) @[Rocket.scala 285:13 288:20 291:24]
    skip
    node _GEN_21 = mux(id_xcpt, _GEN_16, id_ctrl_sel_alu2) @[Rocket.scala 285:13 288:20]
    node _GEN_22 = mux(id_xcpt, _GEN_17, ibuf_RVCExpander__T_14) @[Rocket.scala 286:16 288:20]
    node _T_3742 = or(id_ctrl_fence_i, id_csr_flush) @[Rocket.scala 298:42]
    node _T_3743 = or(_T_3742, csr__T_2334) @[Rocket.scala 298:58]
    skip
    node _T_3744 = and(id_ctrl_jalr, csr_reg_debug) @[Rocket.scala 301:24]
    node _GEN_23 = or(_T_3744, _T_3743) @[Rocket.scala 298:23 301:48 302:25]
    node _GEN_24 = or(_T_3744, id_ctrl_fence_i) @[Rocket.scala 285:13 301:48 303:23]
    node _T_3747 = or(id_bypass_src_0_0, id_bypass_src_0_1) @[Rocket.scala 307:48]
    node _T_3748 = or(_T_3747, id_bypass_src_0_2) @[Rocket.scala 307:48]
    node _T_3749 = or(_T_3748, id_bypass_src_0_3) @[Rocket.scala 307:48]
    node _T_3754 = mux(id_bypass_src_0_2, UInt<2>("h2"), UInt<2>("h3")) @[Mux.scala 31:69]
    node _T_3755 = mux(id_bypass_src_0_1, UInt<2>("h1"), _T_3754) @[Mux.scala 31:69]
    node _T_3756 = mux(id_bypass_src_0_0, UInt<2>("h0"), _T_3755) @[Mux.scala 31:69]
    node _T_3758 = not(_T_3749) @[Rocket.scala 311:26]
    node _T_3759 = and(id_ctrl_rxs1, _T_3758) @[Rocket.scala 311:23]
    node wb_wen = and(wb_valid, wb_ctrl_wxd) @[Rocket.scala 451:25]
    skip
    node ll_wen = or(_T_4183, div__T_680) @[Rocket.scala 442:44 447:12]
    skip
    node rf_wen = or(wb_wen, ll_wen) @[Rocket.scala 452:23]
    node dmem_resp_waddr = bits(io_dmem_resp_bits_tag, 5, 1) @[Rocket.scala 425:46]
    skip
    node ll_waddr = mux(_T_4183, dmem_resp_waddr, div_req_tag) @[Rocket.scala 442:44 446:14]
    skip
    node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) @[Rocket.scala 453:21]
    node _T_4197 = neq(rf_waddr, UInt<5>("h0")) @[Rocket.scala 694:16]
    node _T_4201 = eq(rf_waddr, ibuf_RVCExpander__T_1859_rs1) @[Rocket.scala 697:20]
    node _T_4191 = and(dmem_resp_valid, dmem_resp_xpu) @[Rocket.scala 454:38]
    skip
    skip
    node _T_4193 = neq(wb_ctrl_csr, UInt<3>("h0")) @[Rocket.scala 456:34]
    node _T_4194 = mux(_T_4193, csr__T_2859, wb_reg_wdata) @[Rocket.scala 456:21]
    node _T_4195 = mux(ll_wen, div__T_707, _T_4194) @[Rocket.scala 455:21]
    node rf_wdata = mux(_T_4191, io_dmem_resp_bits_data, _T_4195) @[Rocket.scala 454:21]
    node _GEN_156 = mux(_T_4201, rf_wdata, _T_3341) @[Rocket.scala 689:19 697:{31,39}]
    node _GEN_163 = mux(_T_4197, _GEN_156, _T_3341) @[Rocket.scala 689:19 694:29]
    node id_rs_0 = mux(rf_wen, _GEN_163, _T_3341) @[Rocket.scala 458:17 689:19]
    skip
    node _T_3760 = bits(id_rs_0, 1, 0) @[Rocket.scala 312:37]
    node _T_3761 = shr(id_rs_0, 2) @[Rocket.scala 313:38]
    node _GEN_25 = mux(_T_3759, _T_3760, _T_3756) @[Rocket.scala 310:24 311:38 312:26]
    node _GEN_26 = mux(_T_3759, _T_3761, ex_reg_rs_msb_0) @[Rocket.scala 249:26 311:38 313:26]
    node _T_3762 = or(id_bypass_src_1_0, id_bypass_src_1_1) @[Rocket.scala 307:48]
    node _T_3763 = or(_T_3762, id_bypass_src_1_2) @[Rocket.scala 307:48]
    node _T_3764 = or(_T_3763, id_bypass_src_1_3) @[Rocket.scala 307:48]
    node _T_3769 = mux(id_bypass_src_1_2, UInt<2>("h2"), UInt<2>("h3")) @[Mux.scala 31:69]
    node _T_3770 = mux(id_bypass_src_1_1, UInt<2>("h1"), _T_3769) @[Mux.scala 31:69]
    node _T_3771 = mux(id_bypass_src_1_0, UInt<2>("h0"), _T_3770) @[Mux.scala 31:69]
    node _T_3773 = not(_T_3764) @[Rocket.scala 311:26]
    node _T_3774 = and(id_ctrl_rxs2, _T_3773) @[Rocket.scala 311:23]
    node _T_4202 = eq(rf_waddr, ibuf_RVCExpander__T_1859_rs2) @[Rocket.scala 697:20]
    node _GEN_157 = mux(_T_4202, rf_wdata, _T_3351) @[Rocket.scala 689:19 697:{31,39}]
    node _GEN_164 = mux(_T_4197, _GEN_157, _T_3351) @[Rocket.scala 689:19 694:29]
    node id_rs_1 = mux(rf_wen, _GEN_164, _T_3351) @[Rocket.scala 458:17 689:19]
    skip
    node _T_3775 = bits(id_rs_1, 1, 0) @[Rocket.scala 312:37]
    node _T_3776 = shr(id_rs_1, 2) @[Rocket.scala 313:38]
    node _GEN_27 = mux(_T_3774, _T_3775, _T_3771) @[Rocket.scala 310:24 311:38 312:26]
    node _GEN_28 = mux(_T_3774, _T_3776, ex_reg_rs_msb_1) @[Rocket.scala 249:26 311:38 313:26]
    skip
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    node _T_4324 = and(mem_reg_valid, data_hazard_mem) @[Rocket.scala 506:32]
    node id_load_use = and(_T_4324, mem_ctrl_mem) @[Rocket.scala 506:51]
    skip
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    skip
    node _T_3779 = or(_T_3444, csr__GEN_2) @[Rocket.scala 317:21]
    node _T_3780 = or(_T_3779, ibuf__T_527) @[Rocket.scala 317:41]
    skip
    skip
    node _T_3785 = not(io_dmem_req_ready) @[Rocket.scala 325:45]
    node _T_3786 = and(ex_ctrl_mem, _T_3785) @[Rocket.scala 325:42]
    node _T_3788 = not(div__T_709) @[Rocket.scala 326:45]
    node _T_3789 = and(ex_ctrl_div, _T_3788) @[Rocket.scala 326:42]
    node replay_ex_structural = or(_T_3786, _T_3789) @[Rocket.scala 325:64]
    node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) @[Rocket.scala 327:43]
    node _T_3790 = or(replay_ex_structural, replay_ex_load_use) @[Rocket.scala 328:75]
    node _T_3791 = and(ex_reg_valid, _T_3790) @[Rocket.scala 328:50]
    node replay_ex = or(ex_reg_replay, _T_3791) @[Rocket.scala 328:33]
    node _T_3792 = or(take_pc_mem_wb, replay_ex) @[Rocket.scala 329:35]
    node _T_3794 = not(ex_reg_valid) @[Rocket.scala 329:51]
    node ctrl_killx = or(_T_3792, _T_3794) @[Rocket.scala 329:48]
    node _T_3796 = eq(ex_ctrl_mem_cmd, UInt<5>("h7")) @[Rocket.scala 331:40]
    skip
    node _T_3810 = eq(UInt<3>("h0"), ex_ctrl_mem_type) @[Rocket.scala 331:91]
    skip
    node _T_3811 = eq(UInt<3>("h4"), ex_ctrl_mem_type) @[Rocket.scala 331:91]
    skip
    node _T_3812 = eq(UInt<3>("h1"), ex_ctrl_mem_type) @[Rocket.scala 331:91]
    skip
    node _T_3813 = eq(UInt<3>("h5"), ex_ctrl_mem_type) @[Rocket.scala 331:91]
    skip
    node _T_3816 = or(_T_3810, _T_3811) @[Rocket.scala 331:91]
    node _T_3817 = or(_T_3816, _T_3812) @[Rocket.scala 331:91]
    node _T_3818 = or(_T_3817, _T_3813) @[Rocket.scala 331:91]
    node ex_slow_bypass = or(_T_3796, _T_3818) @[Rocket.scala 331:50]
    node ex_xcpt = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) @[Rocket.scala 334:28]
    node _T_3819 = or(mem_reg_valid, mem_reg_replay) @[Rocket.scala 337:36]
    node mem_pc_valid = or(_T_3819, mem_reg_xcpt_interrupt) @[Rocket.scala 337:54]
    skip
    skip
    node _T_4037 = bits(mem_npc, 1, 1) @[Rocket.scala 345:66]
    node mem_npc_misaligned = and(_T_3489, _T_4037) @[Rocket.scala 345:56]
    node _T_4039 = not(mem_reg_xcpt) @[Rocket.scala 346:27]
    node _T_4040 = xor(mem_ctrl_jalr, mem_npc_misaligned) @[Rocket.scala 346:59]
    node _T_4041 = and(_T_4039, _T_4040) @[Rocket.scala 346:41]
    node _T_4042 = asSInt(mem_reg_wdata) @[Rocket.scala 346:111]
    node _T_4043 = mux(_T_4041, pad(mem_br_target, 64), _T_4042) @[Rocket.scala 346:26]
    node mem_int_wdata = asUInt(_T_4043) @[Rocket.scala 346:119]
    node _T_4044 = or(mem_ctrl_branch, mem_ctrl_jalr) @[Rocket.scala 347:33]
    node mem_cfi = or(_T_4044, mem_ctrl_jal) @[Rocket.scala 347:50]
    skip
    node _T_4046 = or(_T_3821, mem_ctrl_jalr) @[Rocket.scala 348:57]
    skip
    node mem_cfi_taken = or(_T_4046, mem_ctrl_jal) @[Rocket.scala 348:74]
    skip
    skip
    skip
    node _T_4054 = not(ctrl_killx) @[Rocket.scala 353:20]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    node _T_4065 = eq(ex_ctrl_mem_cmd, UInt<5>("h0")) @[Consts.scala 35:31]
    node _T_4067 = eq(ex_ctrl_mem_cmd, UInt<5>("h6")) @[Consts.scala 35:48]
    node _T_4068 = or(_T_4065, _T_4067) @[Consts.scala 35:41]
    skip
    node _T_4071 = or(_T_4068, _T_3796) @[Consts.scala 35:58]
    node _T_4072 = bits(ex_ctrl_mem_cmd, 3, 3) @[Consts.scala 33:29]
    node _T_4074 = eq(ex_ctrl_mem_cmd, UInt<5>("h4")) @[Consts.scala 33:40]
    node _T_4075 = or(_T_4072, _T_4074) @[Consts.scala 33:33]
    node _T_4076 = or(_T_4071, _T_4075) @[Consts.scala 35:75]
    node _T_4077 = and(ex_ctrl_mem, _T_4076) @[Rocket.scala 362:33]
    node _T_4079 = eq(ex_ctrl_mem_cmd, UInt<5>("h1")) @[Consts.scala 36:32]
    skip
    node _T_4082 = or(_T_4079, _T_3796) @[Consts.scala 36:42]
    skip
    skip
    skip
    node _T_4087 = or(_T_4082, _T_4075) @[Consts.scala 36:59]
    node _T_4088 = and(ex_ctrl_mem, _T_4087) @[Rocket.scala 363:34]
    node _GEN_68 = mux(ex_reg_btb_hit, ex_reg_btb_resp_taken, mem_reg_btb_resp_taken) @[Rocket.scala 365:27 136:36 365:46]
    node _GEN_69 = mux(ex_reg_btb_hit, ex_reg_btb_resp_mask, mem_reg_btb_resp_mask) @[Rocket.scala 365:27 136:36 365:46]
    node _GEN_70 = mux(ex_reg_btb_hit, ex_reg_btb_resp_bridx, mem_reg_btb_resp_bridx) @[Rocket.scala 365:27 136:36 365:46]
    node _GEN_71 = mux(ex_reg_btb_hit, ex_reg_btb_resp_target, mem_reg_btb_resp_target) @[Rocket.scala 365:27 136:36 365:46]
    node _GEN_72 = mux(ex_reg_btb_hit, ex_reg_btb_resp_entry, mem_reg_btb_resp_entry) @[Rocket.scala 365:27 136:36 365:46]
    node _GEN_73 = mux(ex_reg_btb_hit, ex_reg_btb_resp_bht_history, mem_reg_btb_resp_bht_history) @[Rocket.scala 365:27 136:36 365:46]
    node _GEN_74 = mux(ex_reg_btb_hit, ex_reg_btb_resp_bht_value, mem_reg_btb_resp_bht_value) @[Rocket.scala 365:27 136:36 365:46]
    skip
    node _T_4090 = and(ex_ctrl_rxs2, ex_ctrl_mem) @[Rocket.scala 372:24]
    node _GEN_75 = mux(_T_4090, ex_rs_1, mem_reg_rs2) @[Rocket.scala 372:58 373:19 147:24]
    skip
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    node _T_4091 = and(mem_reg_load, bpu__GEN_0) @[Rocket.scala 377:38]
    skip
    node _T_4092 = and(mem_reg_store, bpu__GEN_2) @[Rocket.scala 377:75]
    node mem_breakpoint = or(_T_4091, _T_4092) @[Rocket.scala 377:57]
    skip
    node _T_4093 = and(mem_reg_load, bpu__GEN_1) @[Rocket.scala 378:44]
    skip
    node _T_4094 = and(mem_reg_store, bpu__GEN_3) @[Rocket.scala 378:82]
    node mem_debug_breakpoint = or(_T_4093, _T_4094) @[Rocket.scala 378:64]
    node _T_4126 = and(mem_ctrl_mem, io_dmem_xcpt_ma_st) @[Rocket.scala 383:19]
    node _T_4128 = and(mem_ctrl_mem, io_dmem_xcpt_ma_ld) @[Rocket.scala 384:19]
    node _T_4130 = and(mem_ctrl_mem, io_dmem_xcpt_pf_st) @[Rocket.scala 385:19]
    node _T_4132 = and(mem_ctrl_mem, io_dmem_xcpt_pf_ld) @[Rocket.scala 386:19]
    node _T_4134 = or(mem_debug_breakpoint, mem_breakpoint) @[Rocket.scala 645:26]
    node _T_4135 = or(_T_4134, mem_npc_misaligned) @[Rocket.scala 645:26]
    node _T_4136 = or(_T_4135, _T_4126) @[Rocket.scala 645:26]
    node _T_4137 = or(_T_4136, _T_4128) @[Rocket.scala 645:26]
    node _T_4138 = or(_T_4137, _T_4130) @[Rocket.scala 645:26]
    node mem_new_xcpt = or(_T_4138, _T_4132) @[Rocket.scala 645:26]
    node _T_4139 = mux(_T_4130, UInt<3>("h7"), UInt<3>("h5")) @[Mux.scala 31:69]
    node _T_4140 = mux(_T_4128, UInt<3>("h4"), _T_4139) @[Mux.scala 31:69]
    node _T_4141 = mux(_T_4126, UInt<3>("h6"), _T_4140) @[Mux.scala 31:69]
    node _T_4142 = mux(mem_npc_misaligned, UInt<3>("h0"), _T_4141) @[Mux.scala 31:69]
    node _T_4143 = mux(mem_breakpoint, UInt<3>("h3"), _T_4142) @[Mux.scala 31:69]
    node mem_new_cause = mux(mem_debug_breakpoint, UInt<4>("hd"), pad(_T_4143, 4)) @[Mux.scala 31:69]
    node _T_4144 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) @[Rocket.scala 389:29]
    node _T_4145 = and(mem_reg_valid, mem_new_xcpt) @[Rocket.scala 390:20]
    node mem_xcpt = or(_T_4144, _T_4145) @[Rocket.scala 645:26]
    node mem_cause = mux(_T_4144, mem_reg_cause, pad(mem_new_cause, 64)) @[Mux.scala 31:69]
    node _T_4147 = and(mem_reg_valid, mem_ctrl_fp) @[Rocket.scala 393:36]
    node fpu_kill_mem = and(_T_4147, io_fpu_nack_mem) @[Rocket.scala 393:51]
    node _T_4148 = or(dcache_kill_mem, mem_reg_replay) @[Rocket.scala 394:37]
    node replay_mem = or(_T_4148, fpu_kill_mem) @[Rocket.scala 394:55]
    skip
    node _T_4156 = or(killm_common, mem_xcpt) @[Rocket.scala 397:33]
    node ctrl_killm = or(_T_4156, fpu_kill_mem) @[Rocket.scala 397:45]
    skip
    node _T_4160 = not(take_pc_wb) @[Rocket.scala 401:34]
    skip
    skip
    skip
    skip
    skip
    node _T_4167 = and(_T_4039, mem_ctrl_fp) @[Rocket.scala 406:39]
    node _T_4168 = and(_T_4167, mem_ctrl_wxd) @[Rocket.scala 406:54]
    node _T_4169 = mux(_T_4168, io_fpu_toint_data, mem_int_wdata) @[Rocket.scala 406:24]
    skip
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    node _T_4246 = dshl(UInt<1>("h1"), ll_waddr) @[Rocket.scala 672:62]
    node _T_4248 = mux(ll_wen, _T_4246, UInt<32>("h0")) @[Rocket.scala 672:49]
    node _T_4249 = not(_T_4248) @[Rocket.scala 664:64]
    node _T_4250 = and(_T_4243, _T_4249) @[Rocket.scala 664:62]
    skip
    node _GEN_172 = mux(ll_wen, _T_4250, _T_4241) @[Rocket.scala 676:{18,23} 668:25]
    node _T_4262 = and(wb_set_sboard, wb_wen) @[Rocket.scala 490:28]
    node _T_4264 = dshl(UInt<1>("h1"), wb_waddr) @[Rocket.scala 672:62]
    node _T_4266 = mux(_T_4262, _T_4264, UInt<32>("h0")) @[Rocket.scala 672:49]
    node _T_4267 = or(_T_4250, _T_4266) @[Rocket.scala 663:60]
    node _T_4268 = or(ll_wen, _T_4262) @[Rocket.scala 675:17]
    node _GEN_173 = mux(_T_4268, _T_4267, _GEN_172) @[Rocket.scala 676:{18,23}]
    node _T_4350 = and(wb_dcache_miss, wb_ctrl_wfd) @[Rocket.scala 515:35]
    node _T_4351 = or(_T_4350, io_fpu_sboard_set) @[Rocket.scala 515:50]
    node _T_4352 = and(_T_4351, wb_valid) @[Rocket.scala 515:72]
    skip
    node _T_4356 = mux(_T_4352, _T_4264, UInt<32>("h0")) @[Rocket.scala 672:49]
    node _T_4357 = or(_T_4348, _T_4356) @[Rocket.scala 663:60]
    skip
    node _GEN_174 = mux(_T_4352, _T_4357, _T_4348) @[Rocket.scala 676:{18,23} 668:25]
    node _T_4359 = and(dmem_resp_replay, _T_4176) @[Rocket.scala 516:38]
    node _T_4361 = dshl(UInt<1>("h1"), dmem_resp_waddr) @[Rocket.scala 672:62]
    node _T_4363 = mux(_T_4359, _T_4361, UInt<32>("h0")) @[Rocket.scala 672:49]
    node _T_4364 = not(_T_4363) @[Rocket.scala 664:64]
    node _T_4365 = and(_T_4357, _T_4364) @[Rocket.scala 664:62]
    node _T_4366 = or(_T_4352, _T_4359) @[Rocket.scala 675:17]
    node _GEN_175 = mux(_T_4366, _T_4365, _GEN_174) @[Rocket.scala 676:{18,23}]
    node _T_4368 = dshl(UInt<1>("h1"), io_fpu_sboard_clra) @[Rocket.scala 672:62]
    node _T_4370 = mux(io_fpu_sboard_clr, _T_4368, UInt<32>("h0")) @[Rocket.scala 672:49]
    node _T_4371 = not(_T_4370) @[Rocket.scala 664:64]
    node _T_4372 = and(_T_4365, _T_4371) @[Rocket.scala 664:62]
    node _T_4373 = or(_T_4366, io_fpu_sboard_clr) @[Rocket.scala 675:17]
    node _GEN_176 = mux(_T_4373, _T_4372, _GEN_175) @[Rocket.scala 676:{18,23}]
    skip
    node _T_4395 = or(io_dmem_req_valid, dcache_blocked) @[Rocket.scala 523:62]
    skip
    skip
    skip
    skip
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    skip
    node _T_4432 = or(wb_reg_xcpt, csr__T_2331) @[Rocket.scala 540:17]
    skip
    skip
    node _T_4436 = mux(replay_wb_common, wb_reg_pc, mem_npc) @[Rocket.scala 541:8]
    skip
    skip
    node _T_4438 = and(wb_reg_valid, wb_ctrl_fence_i) @[Rocket.scala 544:40]
    node _T_4440 = not(io_dmem_s2_nack) @[Rocket.scala 544:62]
    skip
    node _T_4445 = and(mem_reg_replay, mem_reg_btb_hit) @[Rocket.scala 549:47]
    skip
    node _T_4448 = and(mem_reg_valid, _T_4160) @[Rocket.scala 549:85]
    node _T_4450 = not(mem_cfi) @[Rocket.scala 549:123]
    node _T_4451 = or(mem_cfi_taken, _T_4450) @[Rocket.scala 549:120]
    node _T_4452 = and(_T_4451, mem_misprediction) @[Rocket.scala 549:133]
    skip
    skip
    skip
    skip
    node _T_4459 = and(_T_4448, _T_4452) @[Rocket.scala 549:100]
    skip
    node _T_4462 = not(mem_reg_replay) @[Rocket.scala 550:38]
    skip
    skip
    node _T_4465 = bits(mem_reg_inst, 19, 15) @[Rocket.scala 552:68]
    node _T_4468 = and(_T_4465, UInt<5>("h1b")) @[Rocket.scala 552:76]
    node _T_4469 = eq(UInt<5>("h1"), _T_4468) @[Rocket.scala 552:76]
    skip
    node _T_4473 = mux(mem_reg_rvc, UInt<2>("h0"), UInt<2>("h2")) @[Rocket.scala 554:74]
    node _GEN_243 = pad(_T_4473, 40) @[Rocket.scala 554:69]
    node _T_4474 = add(mem_reg_pc, _GEN_243) @[Rocket.scala 554:69]
    node _T_4475 = tail(_T_4474, 1) @[Rocket.scala 554:69]
    node _T_4476 = not(io_imem_btb_update_bits_br_pc) @[Rocket.scala 555:35]
    node _T_4478 = or(_T_4476, UInt<39>("h3")) @[Rocket.scala 555:66]
    skip
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    node _T_4487 = bits(mem_waddr, 0, 0) @[Rocket.scala 567:80]
    skip
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    node ex_dcache_tag = cat(ex_waddr, ex_ctrl_fp) @[Cat.scala 30:58]
    node _T_4495 = shr(ex_rs_0, 38) @[Rocket.scala 653:16]
    node _T_4496 = bits(alu__T_22, 39, 38) @[Rocket.scala 654:15]
    node _T_4497 = asSInt(_T_4496) @[Rocket.scala 654:39]
    node _T_4499 = eq(_T_4495, UInt<26>("h0")) @[Rocket.scala 656:13]
    node _T_4501 = eq(_T_4495, UInt<26>("h1")) @[Rocket.scala 656:30]
    node _T_4502 = or(_T_4499, _T_4501) @[Rocket.scala 656:25]
    node _T_4504 = neq(_T_4497, SInt<2>("h0")) @[Rocket.scala 656:45]
    node _T_4505 = asSInt(_T_4495) @[Rocket.scala 657:13]
    node _T_4507 = eq(_T_4505, SInt<26>("h-1")) @[Rocket.scala 657:20]
    skip
    node _T_4510 = eq(_T_4505, SInt<26>("h-2")) @[Rocket.scala 657:45]
    node _T_4511 = or(_T_4507, _T_4510) @[Rocket.scala 657:33]
    node _T_4513 = eq(_T_4497, SInt<2>("h-1")) @[Rocket.scala 657:61]
    node _T_4514 = bits(_T_4497, 0, 0) @[Rocket.scala 657:76]
    node _T_4515 = mux(_T_4511, _T_4513, _T_4514) @[Rocket.scala 657:10]
    node _T_4516 = mux(_T_4502, _T_4504, _T_4515) @[Rocket.scala 656:10]
    node _T_4517 = bits(alu__T_22, 38, 0) @[Rocket.scala 658:16]
    skip
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    node _T_4521 = and(mem_ctrl_mem, mem_xcpt) @[Rocket.scala 592:22]
    node _T_4523 = not(io_dmem_s1_kill) @[Rocket.scala 592:37]
    node _T_4524 = and(_T_4521, _T_4523) @[Rocket.scala 592:34]
    node _T_4525 = cat(io_dmem_xcpt_pf_ld, io_dmem_xcpt_pf_st) @[Rocket.scala 593:25]
    node _T_4526 = cat(io_dmem_xcpt_ma_ld, io_dmem_xcpt_ma_st) @[Rocket.scala 593:25]
    node _T_4527 = cat(_T_4526, _T_4525) @[Rocket.scala 593:25]
    node _T_4529 = neq(_T_4527, UInt<4>("h0")) @[Rocket.scala 593:32]
    node _T_4530 = or(_T_4529, reset) @[Rocket.scala 593:11]
    node _T_4532 = not(_T_4530) @[Rocket.scala 593:11]
    skip
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    node _T_4574 = bits(wb_reg_inst, 19, 15) @[Rocket.scala 599:58]
    node _T_4575 = bits(wb_reg_inst, 24, 20) @[Rocket.scala 599:58]
    skip
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    node _T_4577 = bits(csr__T_950, 31, 0) @[Rocket.scala 637:32]
    node _T_4579 = mux(rf_wen, rf_waddr, UInt<5>("h0")) @[Rocket.scala 638:13]
    skip
    reg _T_4581 : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), _T_4581) @[Rocket.scala 639:42]
    reg _T_4582 : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), _T_4582) @[Rocket.scala 639:33]
    skip
    reg _T_4584 : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), _T_4584) @[Rocket.scala 640:42]
    reg _T_4585 : UInt<64>, const_clock with :
      reset => (UInt<1>("h0"), _T_4585) @[Rocket.scala 640:33]
    node _T_4587 = not(reset) @[Rocket.scala 636:11]
    skip
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    io_imem_req_valid <= or(take_pc_wb, take_pc_mem) @[Rocket.scala 161:35]
    io_imem_req_bits_pc <= mux(_T_4432, csr__GEN_98, _T_4436) @[Rocket.scala 540:8]
    io_imem_req_bits_speculative <= not(take_pc_wb) @[Rocket.scala 538:35]
    io_imem_resp_ready <= and(ibuf__T_387, ibuf__T_394) @[IBuf.scala 46:40]
    io_imem_btb_update_valid <= or(_T_4445, _T_4459) @[Rocket.scala 549:67]
    io_imem_btb_update_bits_prediction_valid <= mem_reg_btb_hit @[Rocket.scala 556:44]
    io_imem_btb_update_bits_prediction_bits_taken <= mem_reg_btb_resp_taken @[Rocket.scala 557:43]
    io_imem_btb_update_bits_prediction_bits_mask <= mem_reg_btb_resp_mask @[Rocket.scala 557:43]
    io_imem_btb_update_bits_prediction_bits_bridx <= mem_reg_btb_resp_bridx @[Rocket.scala 557:43]
    io_imem_btb_update_bits_prediction_bits_target <= mem_reg_btb_resp_target @[Rocket.scala 557:43]
    io_imem_btb_update_bits_prediction_bits_entry <= mem_reg_btb_resp_entry @[Rocket.scala 557:43]
    io_imem_btb_update_bits_prediction_bits_bht_history <= mem_reg_btb_resp_bht_history @[Rocket.scala 557:43]
    io_imem_btb_update_bits_prediction_bits_bht_value <= mem_reg_btb_resp_bht_value @[Rocket.scala 557:43]
    io_imem_btb_update_bits_pc <= not(_T_4478) @[Rocket.scala 555:33]
    io_imem_btb_update_bits_target <= bits(io_imem_req_bits_pc, 38, 0) @[Rocket.scala 553:34]
    io_imem_btb_update_bits_taken <= UInt<1>("h0")
    io_imem_btb_update_bits_isValid <= and(_T_4462, mem_cfi) @[Rocket.scala 550:54]
    io_imem_btb_update_bits_isJump <= or(mem_ctrl_jal, mem_ctrl_jalr) @[Rocket.scala 551:50]
    io_imem_btb_update_bits_isReturn <= and(mem_ctrl_jalr, _T_4469) @[Rocket.scala 552:53]
    io_imem_btb_update_bits_br_pc <= bits(_T_4475, 38, 0) @[Rocket.scala 554:33]
    io_imem_bht_update_valid <= and(_T_4448, mem_ctrl_branch) @[Rocket.scala 559:60]
    io_imem_bht_update_bits_prediction_valid <= io_imem_btb_update_bits_prediction_valid @[Rocket.scala 563:38]
    io_imem_bht_update_bits_prediction_bits_taken <= io_imem_btb_update_bits_prediction_bits_taken @[Rocket.scala 563:38]
    io_imem_bht_update_bits_prediction_bits_mask <= io_imem_btb_update_bits_prediction_bits_mask @[Rocket.scala 563:38]
    io_imem_bht_update_bits_prediction_bits_bridx <= io_imem_btb_update_bits_prediction_bits_bridx @[Rocket.scala 563:38]
    io_imem_bht_update_bits_prediction_bits_target <= io_imem_btb_update_bits_prediction_bits_target @[Rocket.scala 563:38]
    io_imem_bht_update_bits_prediction_bits_entry <= io_imem_btb_update_bits_prediction_bits_entry @[Rocket.scala 563:38]
    io_imem_bht_update_bits_prediction_bits_bht_history <= io_imem_btb_update_bits_prediction_bits_bht_history @[Rocket.scala 563:38]
    io_imem_bht_update_bits_prediction_bits_bht_value <= io_imem_btb_update_bits_prediction_bits_bht_value @[Rocket.scala 563:38]
    io_imem_bht_update_bits_pc <= io_imem_btb_update_bits_pc @[Rocket.scala 560:30]
    io_imem_bht_update_bits_taken <= bits(mem_reg_wdata, 0, 0) @[Rocket.scala 338:35]
    io_imem_bht_update_bits_mispredict <= mux(ex_pc_valid, _T_4030, _T_4033) @[Rocket.scala 344:26]
    io_imem_ras_update_valid <= and(mem_reg_valid, _T_4160) @[Rocket.scala 565:45]
    io_imem_ras_update_bits_isCall <= and(io_imem_btb_update_bits_isJump, _T_4487) @[Rocket.scala 567:68]
    io_imem_ras_update_bits_isReturn <= io_imem_btb_update_bits_isReturn @[Rocket.scala 568:36]
    io_imem_ras_update_bits_returnAddr <= bits(mem_int_wdata, 38, 0) @[Rocket.scala 566:38]
    io_imem_ras_update_bits_prediction_valid <= io_imem_btb_update_bits_prediction_valid @[Rocket.scala 569:38]
    io_imem_ras_update_bits_prediction_bits_taken <= io_imem_btb_update_bits_prediction_bits_taken @[Rocket.scala 569:38]
    io_imem_ras_update_bits_prediction_bits_mask <= io_imem_btb_update_bits_prediction_bits_mask @[Rocket.scala 569:38]
    io_imem_ras_update_bits_prediction_bits_bridx <= io_imem_btb_update_bits_prediction_bits_bridx @[Rocket.scala 569:38]
    io_imem_ras_update_bits_prediction_bits_target <= io_imem_btb_update_bits_prediction_bits_target @[Rocket.scala 569:38]
    io_imem_ras_update_bits_prediction_bits_entry <= io_imem_btb_update_bits_prediction_bits_entry @[Rocket.scala 569:38]
    io_imem_ras_update_bits_prediction_bits_bht_history <= io_imem_btb_update_bits_prediction_bits_bht_history @[Rocket.scala 569:38]
    io_imem_ras_update_bits_prediction_bits_bht_value <= io_imem_btb_update_bits_prediction_bits_bht_value @[Rocket.scala 569:38]
    io_imem_flush_icache <= and(_T_4438, _T_4440) @[Rocket.scala 544:59]
    io_imem_flush_tlb <= and(csr_system_insn, csr_insn_rs2) @[CSR.scala 416:37]
    io_dmem_req_valid <= and(ex_reg_valid, ex_ctrl_mem) @[Rocket.scala 581:41]
    io_dmem_req_bits_addr <= cat(_T_4516, _T_4517) @[Cat.scala 30:58]
    io_dmem_req_bits_tag <= pad(ex_dcache_tag, 7) @[Rocket.scala 584:25]
    io_dmem_req_bits_cmd <= ex_ctrl_mem_cmd @[Rocket.scala 585:25]
    io_dmem_req_bits_typ <= ex_ctrl_mem_type @[Rocket.scala 586:25]
    io_dmem_req_bits_phys <= UInt<1>("h0") @[Rocket.scala 587:25]
    io_dmem_req_bits_data <= UInt<64>("h0")
    io_dmem_s1_kill <= or(killm_common, mem_breakpoint) @[Rocket.scala 591:35]
    io_dmem_s1_data <= mux(mem_ctrl_fp, io_fpu_store_data, mem_reg_rs2) @[Rocket.scala 590:25]
    io_dmem_invalidate_lr <= wb_reg_xcpt @[Rocket.scala 589:25]
    io_ptw_ptbr_mode <= csr_reg_sptbr_mode @[Rocket.scala 472:15]
    io_ptw_ptbr_asid <= UInt<16>("h0") @[Rocket.scala 472:15]
    io_ptw_ptbr_ppn <= csr_reg_sptbr_ppn @[Rocket.scala 472:15]
    io_ptw_invalidate <= and(csr_system_insn, csr_insn_rs2) @[CSR.scala 416:37]
    io_ptw_status_debug <= csr_reg_debug @[Rocket.scala 474:17]
    io_ptw_status_isa <= bits(csr_reg_misa, 31, 0) @[Rocket.scala 474:17]
    io_ptw_status_prv <= csr_reg_mstatus_prv @[Rocket.scala 474:17]
    io_ptw_status_sd <= eq(csr__T_2335, UInt<2>("h0")) @[CSR.scala 453:32]
    io_ptw_status_zero2 <= UInt<27>("h0") @[Rocket.scala 474:17]
    io_ptw_status_sxl <= UInt<2>("h2") @[Rocket.scala 474:17]
    io_ptw_status_uxl <= UInt<2>("h2") @[Rocket.scala 474:17]
    io_ptw_status_sd_rv32 <= UInt<1>("h0") @[Rocket.scala 474:17]
    io_ptw_status_zero1 <= UInt<8>("h0") @[Rocket.scala 474:17]
    io_ptw_status_tsr <= csr_reg_mstatus_tsr @[Rocket.scala 474:17]
    io_ptw_status_tw <= csr_reg_mstatus_tw @[Rocket.scala 474:17]
    io_ptw_status_tvm <= csr_reg_mstatus_tvm @[Rocket.scala 474:17]
    io_ptw_status_mxr <= csr_reg_mstatus_mxr @[Rocket.scala 474:17]
    io_ptw_status_pum <= csr_reg_mstatus_pum @[Rocket.scala 474:17]
    io_ptw_status_mprv <= csr_reg_mstatus_mprv @[Rocket.scala 474:17]
    io_ptw_status_xs <= UInt<2>("h0") @[Rocket.scala 474:17]
    io_ptw_status_fs <= csr_reg_mstatus_fs @[Rocket.scala 474:17]
    io_ptw_status_mpp <= csr_reg_mstatus_mpp @[Rocket.scala 474:17]
    io_ptw_status_hpp <= UInt<2>("h0") @[Rocket.scala 474:17]
    io_ptw_status_spp <= csr_reg_mstatus_spp @[Rocket.scala 474:17]
    io_ptw_status_mpie <= csr_reg_mstatus_mpie @[Rocket.scala 474:17]
    io_ptw_status_hpie <= UInt<1>("h0") @[Rocket.scala 474:17]
    io_ptw_status_spie <= csr_reg_mstatus_spie @[Rocket.scala 474:17]
    io_ptw_status_upie <= UInt<1>("h0") @[Rocket.scala 474:17]
    io_ptw_status_mie <= csr_reg_mstatus_mie @[Rocket.scala 474:17]
    io_ptw_status_hie <= UInt<1>("h0") @[Rocket.scala 474:17]
    io_ptw_status_sie <= csr_reg_mstatus_sie @[Rocket.scala 474:17]
    io_ptw_status_uie <= UInt<1>("h0") @[Rocket.scala 474:17]
    io_fpu_inst <= mux(ibuf_RVCExpander__T_1558, ibuf_RVCExpander__T_1703_bits, ibuf_RVCExpander__T_1853_bits) @[Package.scala 19:12]
    io_fpu_fromint_data <= mux(ex_reg_rs_bypass_0, _GEN_3, _T_3605) @[Rocket.scala 251:14]
    io_fpu_fcsr_rm <= csr_reg_frm @[Rocket.scala 467:18]
    io_fpu_dmem_resp_val <= and(dmem_resp_valid, _T_4176) @[Rocket.scala 576:43]
    io_fpu_dmem_resp_type <= io_dmem_resp_bits_typ @[Rocket.scala 578:25]
    io_fpu_dmem_resp_tag <= bits(io_dmem_resp_bits_tag, 5, 1) @[Rocket.scala 425:46]
    io_fpu_dmem_resp_data <= io_dmem_resp_bits_data_word_bypass @[Rocket.scala 577:25]
    io_fpu_valid <= and(_T_3444, id_ctrl_fp) @[Rocket.scala 571:31]
    io_fpu_killx <= or(_T_3792, _T_3794) @[Rocket.scala 329:48]
    io_fpu_killm <= or(_T_4150, _T_4152) @[Rocket.scala 395:68]
    io_rocc_cmd_valid <= UInt<1>("h0") @[Rocket.scala 596:53]
    io_rocc_cmd_bits_inst_funct <= bits(wb_reg_inst, 31, 25) @[Rocket.scala 599:58]
    io_rocc_cmd_bits_inst_rs2 <= bits(wb_reg_inst, 24, 20) @[Rocket.scala 599:58]
    io_rocc_cmd_bits_inst_rs1 <= bits(wb_reg_inst, 19, 15) @[Rocket.scala 599:58]
    io_rocc_cmd_bits_inst_xd <= bits(wb_reg_inst, 14, 14) @[Rocket.scala 599:58]
    io_rocc_cmd_bits_inst_xs1 <= bits(wb_reg_inst, 13, 13) @[Rocket.scala 599:58]
    io_rocc_cmd_bits_inst_xs2 <= bits(wb_reg_inst, 12, 12) @[Rocket.scala 599:58]
    io_rocc_cmd_bits_inst_rd <= bits(wb_reg_inst, 11, 7) @[Rocket.scala 599:58]
    io_rocc_cmd_bits_inst_opcode <= bits(wb_reg_inst, 6, 0) @[Rocket.scala 599:58]
    io_rocc_cmd_bits_rs1 <= wb_reg_wdata @[Rocket.scala 600:24]
    io_rocc_cmd_bits_rs2 <= UInt<64>("h0") @[Rocket.scala 601:24]
    io_rocc_cmd_bits_status_debug <= csr_reg_debug @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_isa <= bits(csr_reg_misa, 31, 0) @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_prv <= csr_reg_mstatus_prv @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_sd <= eq(csr__T_2335, UInt<2>("h0")) @[CSR.scala 453:32]
    io_rocc_cmd_bits_status_zero2 <= UInt<27>("h0") @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_sxl <= UInt<2>("h2") @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_uxl <= UInt<2>("h2") @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_sd_rv32 <= UInt<1>("h0") @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_zero1 <= UInt<8>("h0") @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_tsr <= csr_reg_mstatus_tsr @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_tw <= csr_reg_mstatus_tw @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_tvm <= csr_reg_mstatus_tvm @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_mxr <= csr_reg_mstatus_mxr @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_pum <= csr_reg_mstatus_pum @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_mprv <= csr_reg_mstatus_mprv @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_xs <= UInt<2>("h0") @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_fs <= csr_reg_mstatus_fs @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_mpp <= csr_reg_mstatus_mpp @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_hpp <= UInt<2>("h0") @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_spp <= csr_reg_mstatus_spp @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_mpie <= csr_reg_mstatus_mpie @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_hpie <= UInt<1>("h0") @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_spie <= csr_reg_mstatus_spie @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_upie <= UInt<1>("h0") @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_mie <= csr_reg_mstatus_mie @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_hie <= UInt<1>("h0") @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_sie <= csr_reg_mstatus_sie @[Rocket.scala 598:27]
    io_rocc_cmd_bits_status_uie <= UInt<1>("h0") @[Rocket.scala 598:27]
    io_rocc_resp_ready <= UInt<1>("h0")
    io_rocc_mem_req_ready <= UInt<1>("h0")
    io_rocc_mem_s2_nack <= UInt<1>("h0")
    io_rocc_mem_acquire <= UInt<1>("h0")
    io_rocc_mem_release <= UInt<1>("h0")
    io_rocc_mem_resp_valid <= UInt<1>("h0")
    io_rocc_mem_resp_bits_addr <= UInt<40>("h0")
    io_rocc_mem_resp_bits_tag <= UInt<7>("h0")
    io_rocc_mem_resp_bits_cmd <= UInt<5>("h0")
    io_rocc_mem_resp_bits_typ <= UInt<3>("h0")
    io_rocc_mem_resp_bits_data <= UInt<64>("h0")
    io_rocc_mem_resp_bits_replay <= UInt<1>("h0")
    io_rocc_mem_resp_bits_has_data <= UInt<1>("h0")
    io_rocc_mem_resp_bits_data_word_bypass <= UInt<64>("h0")
    io_rocc_mem_resp_bits_store_data <= UInt<64>("h0")
    io_rocc_mem_replay_next <= UInt<1>("h0")
    io_rocc_mem_xcpt_ma_ld <= UInt<1>("h0")
    io_rocc_mem_xcpt_ma_st <= UInt<1>("h0")
    io_rocc_mem_xcpt_pf_ld <= UInt<1>("h0")
    io_rocc_mem_xcpt_pf_st <= UInt<1>("h0")
    io_rocc_mem_ordered <= UInt<1>("h0")
    io_rocc_exception <= UInt<1>("h0") @[Rocket.scala 597:32]
    node _GEN_244 = mux(reset, UInt<2>("h0"), ibuf__GEN_29) @[IBuf.scala 35:{47,47}]
    ibuf_nBufValid <= bits(_GEN_244, 0, 0) @[IBuf.scala 35:{47,47}]
    skip
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    skip
    ibuf_buf_pc <= mux(ibuf__T_411, ibuf__T_429, ibuf_buf_pc) @[IBuf.scala 56:90 61:14 36:16]
    ibuf_buf_data <= mux(ibuf__T_411, pad(ibuf__T_422, 32), ibuf_buf_data) @[IBuf.scala 36:16 56:90 60:16]
    skip
    ibuf_buf_xcpt_if <= mux(ibuf__T_411, io_imem_resp_bits_xcpt_if, ibuf_buf_xcpt_if) @[IBuf.scala 56:90 59:11 36:16]
    ibuf_buf_replay <= mux(ibuf__T_411, io_imem_resp_bits_replay, ibuf_buf_replay) @[IBuf.scala 56:90 59:11 36:16]
    ibuf_ibufBTBHit <= mux(ibuf__T_411, io_imem_resp_bits_btb_valid, ibuf_ibufBTBHit) @[IBuf.scala 56:90 62:18 37:23]
    ibuf_ibufBTBResp_taken <= mux(ibuf__T_411, ibuf__GEN_0, ibuf_ibufBTBResp_taken) @[IBuf.scala 38:24 56:90]
    ibuf_ibufBTBResp_mask <= mux(ibuf__T_411, ibuf__GEN_1, ibuf_ibufBTBResp_mask) @[IBuf.scala 38:24 56:90]
    ibuf_ibufBTBResp_bridx <= bits(ibuf__GEN_24, 0, 0)
    ibuf_ibufBTBResp_target <= mux(ibuf__T_411, ibuf__GEN_3, ibuf_ibufBTBResp_target) @[IBuf.scala 38:24 56:90]
    ibuf_ibufBTBResp_entry <= mux(ibuf__T_411, ibuf__GEN_4, ibuf_ibufBTBResp_entry) @[IBuf.scala 38:24 56:90]
    ibuf_ibufBTBResp_bht_history <= mux(ibuf__T_411, ibuf__GEN_5, ibuf_ibufBTBResp_bht_history) @[IBuf.scala 38:24 56:90]
    ibuf_ibufBTBResp_bht_value <= mux(ibuf__T_411, ibuf__GEN_6, ibuf_ibufBTBResp_bht_value) @[IBuf.scala 38:24 56:90]
    _T_3331__T_3340_addr <= not(ibuf_RVCExpander__T_1859_rs1) @[Rocket.scala 683:39]
    _T_3331__T_3340_en <= UInt<1>("h1")
    _T_3331__T_3350_addr <= not(ibuf_RVCExpander__T_1859_rs2) @[Rocket.scala 683:39]
    _T_3331__T_3350_en <= UInt<1>("h1")
    _T_3331__T_4200_addr <= not(rf_waddr) @[Rocket.scala 683:39]
    _T_3331__T_4200_en <= and(rf_wen, _T_4197) @[Rocket.scala 458:17 682:23]
    _T_3331__T_4200_data <= mux(_T_4191, io_dmem_resp_bits_data, _T_4195) @[Rocket.scala 454:21]
    _T_3331__T_4200_mask <= UInt<1>("h1") @[Rocket.scala 694:29 695:20]
    skip
    skip
    csr_reg_mstatus_prv <= mux(reset, UInt<2>("h3"), csr__T_467) @[CSR.scala 197:{24,24} 200:19]
    skip
    skip
    skip
    skip
    skip
    skip
    csr_reg_mstatus_tsr <= mux(reset, UInt<1>("h0"), csr__GEN_275) @[CSR.scala 197:{24,24}]
    csr_reg_mstatus_tw <= mux(reset, UInt<1>("h0"), csr__GEN_273) @[CSR.scala 197:{24,24}]
    csr_reg_mstatus_tvm <= mux(reset, UInt<1>("h0"), csr__GEN_274) @[CSR.scala 197:{24,24}]
    csr_reg_mstatus_mxr <= mux(reset, UInt<1>("h0"), csr__GEN_268) @[CSR.scala 197:{24,24}]
    csr_reg_mstatus_pum <= mux(reset, UInt<1>("h0"), csr__GEN_269) @[CSR.scala 197:{24,24}]
    csr_reg_mstatus_mprv <= mux(reset, UInt<1>("h0"), csr__GEN_266) @[CSR.scala 197:{24,24}]
    skip
    csr_reg_mstatus_fs <= mux(reset, UInt<2>("h0"), csr__GEN_276) @[CSR.scala 197:{24,24}]
    csr_reg_mstatus_mpp <= mux(reset, UInt<2>("h3"), csr__GEN_267) @[CSR.scala 197:{24,24}]
    skip
    node _GEN_245 = mux(reset, UInt<2>("h0"), csr__GEN_270) @[CSR.scala 197:{24,24}]
    csr_reg_mstatus_spp <= bits(_GEN_245, 0, 0) @[CSR.scala 197:{24,24}]
    csr_reg_mstatus_mpie <= mux(reset, UInt<1>("h0"), csr__GEN_265) @[CSR.scala 197:{24,24}]
    skip
    csr_reg_mstatus_spie <= mux(reset, UInt<1>("h0"), csr__GEN_271) @[CSR.scala 197:{24,24}]
    skip
    csr_reg_mstatus_mie <= mux(reset, UInt<1>("h0"), csr__GEN_264) @[CSR.scala 197:{24,24}]
    skip
    csr_reg_mstatus_sie <= mux(reset, UInt<1>("h0"), csr__GEN_272) @[CSR.scala 197:{24,24}]
    skip
    csr_reg_dcsr_prv <= mux(reset, UInt<2>("h3"), csr__GEN_297) @[CSR.scala 205:{21,21}]
    csr_reg_singleStepped <= mux(csr__T_1201, UInt<1>("h0"), csr__GEN_38) @[CSR.scala 469:{25,45}]
    csr_reg_dcsr_ebreakm <= mux(reset, UInt<1>("h0"), csr__GEN_294) @[CSR.scala 205:{21,21}]
    skip
    csr_reg_dcsr_ebreaks <= mux(reset, UInt<1>("h0"), csr__GEN_295) @[CSR.scala 205:{21,21}]
    csr_reg_dcsr_ebreaku <= mux(reset, UInt<1>("h0"), csr__GEN_296) @[CSR.scala 205:{21,21}]
    csr_reg_debug <= mux(reset, UInt<1>("h0"), csr__GEN_99) @[CSR.scala 232:{22,22}]
    csr_reg_mideleg <= mux(csr__T_2870, csr__GEN_159, csr_reg_mideleg) @[CSR.scala 242:24 536:49]
    csr_reg_medeleg <= mux(csr__T_2870, csr__GEN_160, csr_reg_medeleg) @[CSR.scala 243:24 536:49]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    csr_reg_dcsr_cause <= mux(reset, UInt<3>("h0"), csr__GEN_62) @[CSR.scala 205:{21,21}]
    csr_reg_dcsr_debugint <= mux(reset, UInt<1>("h0"), io_interrupts_debug) @[CSR.scala 205:{21,21} 660:21]
    skip
    csr_reg_dcsr_halt <= mux(reset, UInt<1>("h0"), csr__GEN_292) @[CSR.scala 205:{21,21}]
    csr_reg_dcsr_step <= mux(reset, UInt<1>("h0"), csr__GEN_293) @[CSR.scala 205:{21,21}]
    csr_reg_dpc <= bits(csr__GEN_298, 39, 0)
    csr_reg_dscratch <= mux(csr__T_2870, csr__GEN_141, csr_reg_dscratch) @[CSR.scala 235:25 536:49]
    skip
    skip
    csr_reg_bp_0_control_dmode <= mux(reset, UInt<1>("h0"), csr__GEN_314) @[CSR.scala 685:18 687:17]
    skip
    skip
    csr_reg_bp_0_control_action <= mux(reset, UInt<1>("h0"), csr__GEN_320) @[CSR.scala 685:18 686:18]
    skip
    skip
    csr_reg_bp_0_control_tmatch <= mux(csr__T_2870, csr__GEN_246, csr_reg_bp_0_control_tmatch) @[CSR.scala 239:19 536:49]
    csr_reg_bp_0_control_m <= mux(csr__T_2870, csr__GEN_248, csr_reg_bp_0_control_m) @[CSR.scala 239:19 536:49]
    skip
    csr_reg_bp_0_control_s <= mux(csr__T_2870, csr__GEN_252, csr_reg_bp_0_control_s) @[CSR.scala 239:19 536:49]
    csr_reg_bp_0_control_u <= mux(csr__T_2870, csr__GEN_254, csr_reg_bp_0_control_u) @[CSR.scala 239:19 536:49]
    csr_reg_bp_0_control_x <= mux(reset, UInt<1>("h0"), csr__GEN_336) @[CSR.scala 685:18 690:13]
    csr_reg_bp_0_control_w <= mux(reset, UInt<1>("h0"), csr__GEN_338) @[CSR.scala 685:18 689:13]
    csr_reg_bp_0_control_r <= mux(reset, UInt<1>("h0"), csr__GEN_340) @[CSR.scala 685:18 688:13]
    csr_reg_bp_0_address <= mux(csr__T_2870, csr__GEN_262, csr_reg_bp_0_address) @[CSR.scala 239:19 536:49]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    csr_reg_mie <= mux(csr__T_2870, csr__GEN_153, csr_reg_mie) @[CSR.scala 241:20 536:49]
    skip
    csr_reg_mip_meip <= io_interrupts_meip @[CSR.scala 659:11]
    skip
    csr_reg_mip_seip <= io_interrupts_seip @[CSR.scala 659:11]
    skip
    csr_reg_mip_mtip <= io_interrupts_mtip @[CSR.scala 659:11]
    skip
    csr_reg_mip_stip <= mux(csr__T_2870, csr__GEN_119, csr_reg_mip_stip) @[CSR.scala 244:20 536:49]
    skip
    csr_reg_mip_msip <= io_interrupts_msip @[CSR.scala 659:11]
    skip
    csr_reg_mip_ssip <= mux(csr__T_2870, csr__GEN_147, csr_reg_mip_ssip) @[CSR.scala 244:20 536:49]
    skip
    csr_reg_mepc <= bits(csr__GEN_281, 39, 0)
    csr_reg_mcause <= mux(csr__T_2870, csr__GEN_124, csr__GEN_72) @[CSR.scala 536:49]
    csr_reg_mbadaddr <= mux(csr__T_2870, csr__GEN_125, csr__GEN_73) @[CSR.scala 536:49]
    csr_reg_mscratch <= mux(csr__T_2870, csr__GEN_122, csr_reg_mscratch) @[CSR.scala 248:25 536:49]
    node _GEN_246 = mux(reset, UInt<64>("h0"), csr__GEN_283) @[CSR.scala 251:{27,27}]
    csr_reg_mtvec <= bits(_GEN_246, 31, 0) @[CSR.scala 251:{27,27}]
    csr_reg_mcounteren <= bits(csr__GEN_310, 31, 0)
    csr_reg_scounteren <= bits(csr__GEN_309, 31, 0)
    csr_reg_sepc <= bits(csr__GEN_303, 39, 0)
    csr_reg_scause <= mux(csr__T_2870, csr__GEN_157, csr__GEN_65) @[CSR.scala 536:49]
    csr_reg_sbadaddr <= mux(csr__T_2870, csr__GEN_158, csr__GEN_66) @[CSR.scala 536:49]
    csr_reg_sscratch <= mux(csr__T_2870, csr__GEN_154, csr_reg_sscratch) @[CSR.scala 261:25 536:49]
    csr_reg_stvec <= bits(csr__GEN_304, 38, 0)
    csr_reg_sptbr_mode <= mux(csr__T_2870, csr__GEN_151, csr_reg_sptbr_mode) @[CSR.scala 263:22 536:49]
    skip
    csr_reg_sptbr_ppn <= mux(csr__T_2870, csr__GEN_152, csr_reg_sptbr_ppn) @[CSR.scala 263:22 536:49]
    csr_reg_wfi <= mux(reset, UInt<1>("h0"), csr__GEN_37) @[CSR.scala 264:{20,20}]
    csr_reg_fflags <= bits(csr__GEN_290, 4, 0)
    csr_reg_frm <= bits(csr__GEN_291, 2, 0)
    node _GEN_247 = mux(reset, UInt<64>("h0"), csr__GEN_288) @[Counters.scala 47:{37,37}]
    csr__T_931 <= bits(_GEN_247, 5, 0) @[Counters.scala 47:{37,37}]
    csr__T_934 <= mux(reset, UInt<58>("h0"), csr__GEN_289) @[Counters.scala 52:{27,27}]
    node _GEN_248 = mux(reset, UInt<64>("h0"), csr__GEN_286) @[Counters.scala 47:{37,37}]
    csr__T_942 <= bits(_GEN_248, 5, 0) @[Counters.scala 47:{37,37}]
    csr__T_945 <= mux(reset, UInt<58>("h0"), csr__GEN_287) @[Counters.scala 52:{27,27}]
    csr_reg_misa <= mux(reset, UInt<64>("h800000000014112d"), csr__GEN_277) @[CSR.scala 307:{21,21}]
    div_state <= mux(reset, UInt<3>("h0"), div__GEN_22) @[Multiplier.scala 45:{18,18}]
    skip
    div_req_dw <= mux(div__T_682, ex_ctrl_alu_dw, div_req_dw) @[Multiplier.scala 153:24 161:9 47:16]
    skip
    skip
    div_req_tag <= mux(div__T_682, ex_waddr, div_req_tag) @[Multiplier.scala 153:24 161:9 47:16]
    div_count <= mux(div__T_682, UInt<7>("h0"), div__GEN_19) @[Multiplier.scala 153:24 157:11]
    div_neg_out <= mux(div__T_682, div__T_693, div__GEN_20) @[Multiplier.scala 153:24 158:13]
    div_isMul <= mux(div__T_682, div__T_88, div_isMul) @[Multiplier.scala 153:24 155:11 50:18]
    div_isHi <= mux(div__T_682, div__T_100, div_isHi) @[Multiplier.scala 153:24 156:10 51:17]
    div_divisor <= mux(div__T_682, div__T_694, div__GEN_3) @[Multiplier.scala 153:24 159:13]
    div_remainder <= mux(div__T_682, pad(div_lhs_in, 130), div__GEN_17) @[Multiplier.scala 153:24 160:15]
    skip
    ex_ctrl_fp <= mux(_T_3444, id_ctrl_fp, ex_ctrl_fp) @[Rocket.scala 284:22 285:13 115:20]
    skip
    ex_ctrl_branch <= mux(_T_3444, id_ctrl_branch, ex_ctrl_branch) @[Rocket.scala 284:22 285:13 115:20]
    ex_ctrl_jal <= mux(_T_3444, id_ctrl_jal, ex_ctrl_jal) @[Rocket.scala 284:22 285:13 115:20]
    ex_ctrl_jalr <= mux(_T_3444, id_ctrl_jalr, ex_ctrl_jalr) @[Rocket.scala 284:22 285:13 115:20]
    ex_ctrl_rxs2 <= mux(_T_3444, id_ctrl_rxs2, ex_ctrl_rxs2) @[Rocket.scala 284:22 285:13 115:20]
    skip
    ex_ctrl_sel_alu2 <= mux(_T_3444, _GEN_21, ex_ctrl_sel_alu2) @[Rocket.scala 115:20 284:22]
    ex_ctrl_sel_alu1 <= mux(_T_3444, _GEN_20, ex_ctrl_sel_alu1) @[Rocket.scala 115:20 284:22]
    ex_ctrl_sel_imm <= mux(_T_3444, id_ctrl_sel_imm, ex_ctrl_sel_imm) @[Rocket.scala 284:22 285:13 115:20]
    ex_ctrl_alu_dw <= mux(_T_3444, _GEN_19, ex_ctrl_alu_dw) @[Rocket.scala 115:20 284:22]
    ex_ctrl_alu_fn <= mux(_T_3444, _GEN_18, ex_ctrl_alu_fn) @[Rocket.scala 115:20 284:22]
    ex_ctrl_mem <= mux(_T_3444, id_ctrl_mem, ex_ctrl_mem) @[Rocket.scala 284:22 285:13 115:20]
    ex_ctrl_mem_cmd <= mux(_T_3444, id_ctrl_mem_cmd, ex_ctrl_mem_cmd) @[Rocket.scala 284:22 285:13 115:20]
    ex_ctrl_mem_type <= mux(_T_3444, id_ctrl_mem_type, ex_ctrl_mem_type) @[Rocket.scala 284:22 285:13 115:20]
    skip
    skip
    skip
    ex_ctrl_wfd <= mux(_T_3444, id_ctrl_wfd, ex_ctrl_wfd) @[Rocket.scala 284:22 285:13 115:20]
    ex_ctrl_div <= mux(_T_3444, id_ctrl_div, ex_ctrl_div) @[Rocket.scala 284:22 285:13 115:20]
    ex_ctrl_wxd <= mux(_T_3444, id_ctrl_wxd, ex_ctrl_wxd) @[Rocket.scala 284:22 285:13 115:20]
    ex_ctrl_csr <= mux(_T_3444, id_csr, ex_ctrl_csr) @[Rocket.scala 284:22 287:17 115:20]
    ex_ctrl_fence_i <= mux(_T_3444, _GEN_24, ex_ctrl_fence_i) @[Rocket.scala 115:20 284:22]
    skip
    skip
    skip
    skip
    mem_ctrl_fp <= mux(ex_pc_valid, ex_ctrl_fp, mem_ctrl_fp) @[Rocket.scala 359:22 360:14 116:21]
    skip
    mem_ctrl_branch <= mux(ex_pc_valid, ex_ctrl_branch, mem_ctrl_branch) @[Rocket.scala 359:22 360:14 116:21]
    mem_ctrl_jal <= mux(ex_pc_valid, ex_ctrl_jal, mem_ctrl_jal) @[Rocket.scala 359:22 360:14 116:21]
    mem_ctrl_jalr <= mux(ex_pc_valid, ex_ctrl_jalr, mem_ctrl_jalr) @[Rocket.scala 359:22 360:14 116:21]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    mem_ctrl_mem <= mux(ex_pc_valid, ex_ctrl_mem, mem_ctrl_mem) @[Rocket.scala 359:22 360:14 116:21]
    skip
    skip
    skip
    skip
    skip
    mem_ctrl_wfd <= mux(ex_pc_valid, ex_ctrl_wfd, mem_ctrl_wfd) @[Rocket.scala 359:22 360:14 116:21]
    mem_ctrl_div <= mux(ex_pc_valid, ex_ctrl_div, mem_ctrl_div) @[Rocket.scala 359:22 360:14 116:21]
    mem_ctrl_wxd <= mux(ex_pc_valid, ex_ctrl_wxd, mem_ctrl_wxd) @[Rocket.scala 359:22 360:14 116:21]
    mem_ctrl_csr <= mux(ex_pc_valid, ex_ctrl_csr, mem_ctrl_csr) @[Rocket.scala 359:22 360:14 116:21]
    mem_ctrl_fence_i <= mux(ex_pc_valid, ex_ctrl_fence_i, mem_ctrl_fence_i) @[Rocket.scala 359:22 360:14 116:21]
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    skip
    wb_ctrl_mem <= mux(mem_pc_valid, mem_ctrl_mem, wb_ctrl_mem) @[Rocket.scala 404:23 405:13 117:20]
    skip
    skip
    skip
    skip
    skip
    wb_ctrl_wfd <= mux(mem_pc_valid, mem_ctrl_wfd, wb_ctrl_wfd) @[Rocket.scala 404:23 405:13 117:20]
    wb_ctrl_div <= mux(mem_pc_valid, mem_ctrl_div, wb_ctrl_div) @[Rocket.scala 404:23 405:13 117:20]
    wb_ctrl_wxd <= mux(mem_pc_valid, mem_ctrl_wxd, wb_ctrl_wxd) @[Rocket.scala 404:23 405:13 117:20]
    wb_ctrl_csr <= mux(mem_pc_valid, mem_ctrl_csr, wb_ctrl_csr) @[Rocket.scala 404:23 405:13 117:20]
    wb_ctrl_fence_i <= mux(mem_pc_valid, mem_ctrl_fence_i, wb_ctrl_fence_i) @[Rocket.scala 404:23 405:13 117:20]
    skip
    skip
    skip
    ex_reg_xcpt_interrupt <= and(_T_3719, csr__GEN_2) @[Rocket.scala 279:62]
    ex_reg_valid <= not(ctrl_killd) @[Rocket.scala 276:19]
    ex_reg_rvc <= mux(_T_3444, _GEN_22, ex_reg_rvc) @[Rocket.scala 284:22 121:35]
    ex_reg_btb_hit <= or(ibuf__T_519, ibuf__T_563) @[IBuf.scala 104:48]
    ex_reg_btb_resp_taken <= mux(ibuf__T_564, ibuf__T_501_taken, ex_reg_btb_resp_taken) @[Rocket.scala 123:35 282:{39,57}]
    ex_reg_btb_resp_mask <= mux(ibuf__T_564, ibuf__T_501_mask, ex_reg_btb_resp_mask) @[Rocket.scala 123:35 282:{39,57}]
    ex_reg_btb_resp_bridx <= mux(ibuf__T_564, ibuf__T_501_bridx, ex_reg_btb_resp_bridx) @[Rocket.scala 123:35 282:{39,57}]
    ex_reg_btb_resp_target <= mux(ibuf__T_564, ibuf__T_501_target, ex_reg_btb_resp_target) @[Rocket.scala 123:35 282:{39,57}]
    ex_reg_btb_resp_entry <= mux(ibuf__T_564, ibuf__T_501_entry, ex_reg_btb_resp_entry) @[Rocket.scala 123:35 282:{39,57}]
    ex_reg_btb_resp_bht_history <= mux(ibuf__T_564, ibuf__T_501_bht_history, ex_reg_btb_resp_bht_history) @[Rocket.scala 123:35 282:{39,57}]
    ex_reg_btb_resp_bht_value <= mux(ibuf__T_564, ibuf__T_501_bht_value, ex_reg_btb_resp_bht_value) @[Rocket.scala 123:35 282:{39,57}]
    ex_reg_xcpt <= and(_T_3444, id_xcpt) @[Rocket.scala 278:30]
    ex_reg_flush_pipe <= mux(_T_3444, _GEN_23, ex_reg_flush_pipe) @[Rocket.scala 284:22 125:35]
    ex_reg_load_use <= mux(_T_3444, id_load_use, ex_reg_load_use) @[Rocket.scala 284:22 299:21 126:35]
    ex_cause <= mux(id_xcpt, id_cause, ex_cause) @[Rocket.scala 280:{18,33} 127:35]
    ex_reg_replay <= and(_T_3719, ibuf__T_527) @[Rocket.scala 277:54]
    ex_reg_pc <= mux(_T_3780, ibuf__T_512, ex_reg_pc) @[Rocket.scala 317:73 319:15 129:22]
    ex_reg_inst <= mux(_T_3780, ibuf_RVCExpander__T_1859_bits, ex_reg_inst) @[Rocket.scala 317:73 318:17 130:24]
    mem_reg_xcpt_interrupt <= and(_T_3718, ex_reg_xcpt_interrupt) @[Rocket.scala 356:45]
    mem_reg_valid <= not(ctrl_killx) @[Rocket.scala 353:20]
    mem_reg_rvc <= mux(ex_pc_valid, ex_reg_rvc, mem_reg_rvc) @[Rocket.scala 359:22 361:17 134:36]
    mem_reg_btb_hit <= mux(ex_pc_valid, ex_reg_btb_hit, mem_reg_btb_hit) @[Rocket.scala 359:22 364:21 135:36]
    mem_reg_btb_resp_taken <= mux(ex_pc_valid, _GEN_68, mem_reg_btb_resp_taken) @[Rocket.scala 359:22 136:36]
    mem_reg_btb_resp_mask <= mux(ex_pc_valid, _GEN_69, mem_reg_btb_resp_mask) @[Rocket.scala 359:22 136:36]
    mem_reg_btb_resp_bridx <= mux(ex_pc_valid, _GEN_70, mem_reg_btb_resp_bridx) @[Rocket.scala 359:22 136:36]
    mem_reg_btb_resp_target <= mux(ex_pc_valid, _GEN_71, mem_reg_btb_resp_target) @[Rocket.scala 359:22 136:36]
    mem_reg_btb_resp_entry <= mux(ex_pc_valid, _GEN_72, mem_reg_btb_resp_entry) @[Rocket.scala 359:22 136:36]
    mem_reg_btb_resp_bht_history <= mux(ex_pc_valid, _GEN_73, mem_reg_btb_resp_bht_history) @[Rocket.scala 359:22 136:36]
    mem_reg_btb_resp_bht_value <= mux(ex_pc_valid, _GEN_74, mem_reg_btb_resp_bht_value) @[Rocket.scala 359:22 136:36]
    mem_reg_xcpt <= and(_T_4054, ex_xcpt) @[Rocket.scala 355:31]
    mem_reg_replay <= and(_T_3718, replay_ex) @[Rocket.scala 354:37]
    mem_reg_flush_pipe <= mux(ex_pc_valid, ex_reg_flush_pipe, mem_reg_flush_pipe) @[Rocket.scala 359:22 366:24 139:36]
    mem_reg_cause <= mux(ex_xcpt, ex_cause, mem_reg_cause) @[Rocket.scala 357:{18,34} 140:36]
    mem_reg_slow_bypass <= mux(ex_pc_valid, ex_slow_bypass, mem_reg_slow_bypass) @[Rocket.scala 359:22 367:25 141:36]
    mem_reg_load <= mux(ex_pc_valid, _T_4077, mem_reg_load) @[Rocket.scala 359:22 362:18 142:36]
    mem_reg_store <= mux(ex_pc_valid, _T_4088, mem_reg_store) @[Rocket.scala 359:22 363:19 143:36]
    mem_reg_pc <= mux(ex_pc_valid, ex_reg_pc, mem_reg_pc) @[Rocket.scala 359:22 370:16 144:23]
    mem_reg_inst <= mux(ex_pc_valid, ex_reg_inst, mem_reg_inst) @[Rocket.scala 359:22 369:18 145:25]
    mem_reg_wdata <= mux(ex_pc_valid, alu__GEN_0, mem_reg_wdata) @[Rocket.scala 359:22 371:19 146:26]
    mem_reg_rs2 <= mux(ex_pc_valid, _GEN_75, mem_reg_rs2) @[Rocket.scala 359:22 147:24]
    wb_reg_valid <= not(ctrl_killm) @[Rocket.scala 400:19]
    wb_reg_xcpt <= and(mem_xcpt, _T_4160) @[Rocket.scala 402:27]
    wb_reg_replay <= and(replay_mem, _T_4160) @[Rocket.scala 401:31]
    wb_reg_cause <= mux(mem_xcpt, mem_cause, wb_reg_cause) @[Rocket.scala 403:{19,34} 153:35]
    wb_reg_pc <= mux(mem_pc_valid, mem_reg_pc, wb_reg_pc) @[Rocket.scala 404:23 411:15 154:22]
    wb_reg_inst <= mux(mem_pc_valid, mem_reg_inst, wb_reg_inst) @[Rocket.scala 404:23 410:17 155:24]
    wb_reg_wdata <= mux(mem_pc_valid, _T_4169, wb_reg_wdata) @[Rocket.scala 404:23 406:18 156:25]
    skip
    _T_4241 <= mux(reset, UInt<32>("h0"), _GEN_173) @[Rocket.scala 668:{25,25}]
    _T_4348 <= mux(reset, UInt<32>("h0"), _GEN_176) @[Rocket.scala 668:{25,25}]
    dcache_blocked <= and(_T_3785, _T_4395) @[Rocket.scala 523:40]
    skip
    id_reg_fence <= mux(reset, UInt<1>("h0"), _T_3512) @[Rocket.scala 178:{25,25} 211:16]
    ex_reg_rs_bypass_0 <= mux(_T_3444, _T_3749, ex_reg_rs_bypass_0) @[Rocket.scala 284:22 309:27 247:29]
    ex_reg_rs_bypass_1 <= mux(_T_3444, _T_3764, ex_reg_rs_bypass_1) @[Rocket.scala 284:22 309:27 247:29]
    ex_reg_rs_lsb_0 <= mux(_T_3444, _GEN_25, ex_reg_rs_lsb_0) @[Rocket.scala 284:22 248:26]
    ex_reg_rs_lsb_1 <= mux(_T_3444, _GEN_27, ex_reg_rs_lsb_1) @[Rocket.scala 284:22 248:26]
    ex_reg_rs_msb_0 <= mux(_T_3444, _GEN_26, ex_reg_rs_msb_0) @[Rocket.scala 284:22 249:26]
    ex_reg_rs_msb_1 <= mux(_T_3444, _GEN_28, ex_reg_rs_msb_1) @[Rocket.scala 284:22 249:26]
    _T_4154 <= and(div__T_709, div_io_req_valid) @[Decoupled.scala 30:37]
    _T_4581 <= mux(ex_reg_rs_bypass_0, _GEN_3, _T_3605) @[Rocket.scala 251:14]
    _T_4582 <= _T_4581 @[Rocket.scala 639:33]
    _T_4584 <= mux(ex_reg_rs_bypass_1, _GEN_7, _T_3607) @[Rocket.scala 251:14]
    _T_4585 <= _T_4584 @[Rocket.scala 640:33]